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To this purpose, the behavior of the QoS\u2010400 regulators is analytically characterized and then, taking the Xilinx Ultrascale+ as a reference modern heterogeneous platform, a software infrastructure to control such regulators from Linux is proposed. As an experience report, this article presents the results of an extensive experimental evaluation, based on both benchmarks and microbenchmarks, aimed at validating the effectiveness of QoS\u2010400 regulators in predictably controlling I\/O\u2010related memory traffic, as well as assessing the impact of the regulation on software applications and I\/O devices themselves.<\/jats:p>","DOI":"10.1002\/spe.3053","type":"journal-article","created":{"date-parts":[[2021,11,11]],"date-time":"2021-11-11T06:43:47Z","timestamp":1636613027000},"page":"1095-1113","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":21,"title":["Profiling and controlling I\/O\u2010related memory contention in COTS heterogeneous platforms"],"prefix":"10.1002","volume":"52","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0003-2750-7437","authenticated-orcid":false,"given":"Matteo","family":"Zini","sequence":"first","affiliation":[{"name":"TeCIP Institute Scuola Superiore Sant'Anna  Pisa Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giorgiomaria","family":"Cicero","sequence":"additional","affiliation":[{"name":"TeCIP Institute Scuola Superiore Sant'Anna  Pisa Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0003-4719-3631","authenticated-orcid":false,"given":"Daniel","family":"Casini","sequence":"additional","affiliation":[{"name":"TeCIP Institute Scuola Superiore Sant'Anna  Pisa Italy"},{"name":"Department of Excellence in Robotics &amp; AI Scuola Superiore Sant'Anna  Pisa Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alessandro","family":"Biondi","sequence":"additional","affiliation":[{"name":"TeCIP Institute Scuola Superiore Sant'Anna  Pisa Italy"},{"name":"Department of Excellence in Robotics &amp; AI Scuola Superiore Sant'Anna  Pisa Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"311","published-online":{"date-parts":[[2021,11,10]]},"reference":[{"key":"e_1_2_9_2_1","unstructured":"(CAST) CAST. position paper CAST\u201032A: multi\u2010core processors; 2016."},{"key":"e_1_2_9_3_1","doi-asserted-by":"crossref","unstructured":"FarshchiF HuangQ YunH.BRU: bandwidth regulation unit for real\u2010time multicore processors. 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