{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,11,16]],"date-time":"2023-11-16T00:04:29Z","timestamp":1700093069899},"reference-count":12,"publisher":"Wiley","issue":"12","license":[{"start":{"date-parts":[[2007,12,19]],"date-time":"2007-12-19T00:00:00Z","timestamp":1198022400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Softw Pract Exp"],"published-print":{"date-parts":[[2008,10]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper investigates the computational characteristics of the software applications that are developed to support typical modern e\u2010commerce applications. These applications have a significant impact on global commerce, and their influence is expected to continue. We show that the micro\u2010architectural features of the memory subsystem, assisted by the operating system (such as the use of concurrent pageable page sizes), can significantly improve the performance of these applications. In particular, we show that using 64\u2009kB page size in addition to the default 4\u2009kB page size provides substantial throughput improvements for a typical commercial application (Trade6) without adding any complexity for the application developer or the system administrator. Copyright \u00a9 2007 John Wiley &amp; Sons, Ltd.<\/jats:p>","DOI":"10.1002\/spe.866","type":"journal-article","created":{"date-parts":[[2007,12,19]],"date-time":"2007-12-19T17:46:22Z","timestamp":1198086382000},"page":"1261-1272","source":"Crossref","is-referenced-by-count":1,"title":["Effectiveness of multiple pageable page sizes for commercial applications"],"prefix":"10.1002","volume":"38","author":[{"given":"Joefon","family":"Jann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niteesh","family":"Dubey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pratap","family":"Pattnaik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. Sarma","family":"Burugula","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,12,19]]},"reference":[{"key":"e_1_2_1_2_2","unstructured":"WulfW McKeeS. Hitting the memory wall: Implications of the obvious.https:\/\/2.zoppoz.workers.dev:443\/http\/www.cs.virginia.edu\/papers\/Hitting_Memory_Wall\u2010wulf94.pdf[19 November2007]."},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1147\/sj.421.0005"},{"key":"e_1_2_1_4_2","unstructured":"WebSphere Application Server V6.1: Technical Overview.https:\/\/2.zoppoz.workers.dev:443\/http\/www.redbooks.ibm.com\/redpapers\/pdfs\/redp4191.pdf[19 November2007]."},{"key":"e_1_2_1_5_2","unstructured":"DB2 Information Center.https:\/\/2.zoppoz.workers.dev:443\/http\/publib.boulder.ibm.com\/infocenter\/db2luw\/v9\/index.jsp[19 November2007]."},{"key":"e_1_2_1_6_2","unstructured":"IBM WebSphere Performance and Trade6 Benchmark.https:\/\/2.zoppoz.workers.dev:443\/http\/www.ibm.com\/software\/webservers\/appserv\/was\/performance.html[19 November2007]."},{"issue":"2","key":"e_1_2_1_7_2","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1109\/MM.2004.1289290","article-title":"IBM POWER5 chip: A dual\u2010core multithreaded processor","volume":"24","author":"Kalla R","year":"2004","journal-title":"IEEE Micro"},{"issue":"4","key":"e_1_2_1_8_2","first-page":"505","article-title":"POWER5 system microarchitecture","volume":"49","author":"Sinharoy B","year":"2004","journal-title":"IBM Journal of Research and Development"},{"key":"e_1_2_1_9_2","unstructured":"Power ISA Version 2.04 Book III\u2010S: Sections 5.7.5 and 5.7.7.https:\/\/2.zoppoz.workers.dev:443\/http\/www.power.org\/resources\/downloads\/PowerISA_Public.pdf[19 November2007]."},{"key":"e_1_2_1_10_2","volume-title":"The PowerPC Architecture: A Specification for a New Family of Risc Processors","author":"May C","year":"1994"},{"key":"e_1_2_1_11_2","unstructured":"HepkinD. Guide to multiple page size support on AIX 5L version 5.3.https:\/\/2.zoppoz.workers.dev:443\/http\/www.ibm.com\/servers\/aix\/whitepapers\/multiple_page.pdf[19 November2007]."},{"key":"e_1_2_1_12_2","doi-asserted-by":"publisher","DOI":"10.1002\/spe.612"},{"key":"e_1_2_1_13_2","unstructured":"KamathS ShahP. IBM DB2 Enterprise 9 performance with POWER5 + and AIX 5L multipage support.https:\/\/2.zoppoz.workers.dev:443\/http\/www.ibm.com\/developerworks\/db2\/library\/techarticle\/dm\u20100606kamath\/index.html[19 November2007]."}],"container-title":["Software: Practice and Experience"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fspe.866","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/spe.866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,15]],"date-time":"2023-11-15T04:31:12Z","timestamp":1700022672000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/onlinelibrary.wiley.com\/doi\/10.1002\/spe.866"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12,19]]},"references-count":12,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2008,10]]}},"alternative-id":["10.1002\/spe.866"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1002\/spe.866","archive":["Portico"],"relation":{},"ISSN":["0038-0644","1097-024X"],"issn-type":[{"value":"0038-0644","type":"print"},{"value":"1097-024X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,12,19]]}}}