{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:16:48Z","timestamp":1725470208281},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_42","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"439-449","source":"Crossref","is-referenced-by-count":0,"title":["Optimization of Master-Slave Flip-Flops for High-Performance Applications"],"prefix":"10.1007","author":[{"given":"Ra\u00fal","family":"Jim\u00e9nez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pilar","family":"Parra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Castro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"S\u00e1nchez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Acosta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"42_CR1","doi-asserted-by":"publisher","DOI":"10.1002\/0471723703","volume-title":"Digital System Clocking: High-Performance and Low-Power Aspects","author":"V.G. Oklobdzija","year":"2003","unstructured":"Oklobdzija, V.G., Stojanovic, V.M., Markovic, D.M., Nedovic, N.M.: Digital System Clocking: High-Performance and Low-Power Aspects. John Wiley & Sons, Chichester (2003)"},{"key":"42_CR2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-3013-5","volume-title":"Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs","author":"X. Aragon\u00e8s","year":"1999","unstructured":"Aragon\u00e8s, X., Gonz\u00e1lez, J.L., Rubio, A.: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer Academic Publishers, Dordrecht (1999)"},{"key":"42_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"316","DOI":"10.1007\/3-540-45373-3_33","volume-title":"Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation","author":"A.J. Acosta","year":"2000","unstructured":"Acosta, A.J., Jim\u00e9nez, R., Juan, J., Bellido, M.J., Valencia, M.: Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol.\u00a01918, pp. 316\u2013326. Springer, Heidelberg (2000)"},{"issue":"2","key":"42_CR4","doi-asserted-by":"publisher","first-page":"145","DOI":"10.1023\/A:1021216015286","volume":"33","author":"R. Jim\u00e9nez","year":"2002","unstructured":"Jim\u00e9nez, R., Parra, P., Sanmart\u00edn, P., Acosta, A.J.: Analysis of high-performance flip-flops for submicron mixed-signal applications. Int. Journal of Analog Integrated Circuits and Signal Processing\u00a033(2), 145\u2013156 (2002)","journal-title":"Int. Journal of Analog Integrated Circuits and Signal Processing"},{"key":"42_CR5","doi-asserted-by":"publisher","first-page":"1568","DOI":"10.1109\/4.720406","volume":"33","author":"C.Y. Yang","year":"1998","unstructured":"Yang, C.Y., Dehng, G.K., Hsu, J.M., Liu, S.I.: New dynamic flip-flop for high-speed dual-modulus prescaler. IEEE J. Solid-State Circuits\u00a033, 1568\u20131571 (1998)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"42_CR6","doi-asserted-by":"publisher","first-page":"294","DOI":"10.1049\/el:20000268","volume":"36","author":"A.G.M. Strollo","year":"2000","unstructured":"Strollo, A.G.M., De Caro, D.: Low power flip-flop with clock gating on master-slave latches. Electronics Letters\u00a036, 294\u2013295 (2000)","journal-title":"Electronics Letters"},{"key":"42_CR7","doi-asserted-by":"publisher","first-page":"1440","DOI":"10.1109\/4.340417","volume":"29","author":"G. Gerosa","year":"1994","unstructured":"Gerosa, G., Gary, S., Dietz, C., Dac, P., Hoover, K., Alvarez, J., Sanchez, H., Ippolito, P., Tai, N., Litch, S., Eno, J., Golab, J., Vanderschaaf, N., Kahle, J.: A 2.2 W, 80 MHz supescalar RISC microprocessor. IEEE J. Solid-State Circuits\u00a029, 1440\u20131452 (1994)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"42_CR8","volume-title":"Principles of CMOS VLSI Design: A Systems Perspective","author":"N.H. Weste","year":"1994","unstructured":"Weste, N.H., Eshragian, K.: Principles of CMOS VLSI Design: A Systems Perspective, 2nd edn. Addison-Wesley, Reading (1994)","edition":"2"},{"key":"42_CR9","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/4.553179","volume":"32","author":"J. Yuan","year":"1997","unstructured":"Yuan, J., Svensson, C.: New single-clock CMOS latches and flip-flops with improved speed and power savings. IEEE J. Solid-State Circtuis\u00a032, 62\u201369 (1997)","journal-title":"IEEE J. Solid-State Circtuis"},{"key":"42_CR10","unstructured":"Austria Microsystems. 0.35 \u03bcm tech, URL: \n                    \n                      https:\/\/2.zoppoz.workers.dev:443\/http\/www.austriamicrosystems.com"},{"key":"42_CR11","unstructured":"Oskuii, S.T.: Comparative study on low-power high performance flip-flops, Technical Report LiTH-ISY-EX-3432-2003, Link\u00f6ping University (2003)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/link.springer.com\/content\/pdf\/10.1007\/11847083_42.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T07:18:34Z","timestamp":1619507914000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/link.springer.com\/10.1007\/11847083_42"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":11,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/11847083_42","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}