{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T06:10:04Z","timestamp":1742019004331,"version":"3.38.0"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2002,3,1]],"date-time":"2002-03-01T00:00:00Z","timestamp":1014940800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2002,3]]},"DOI":"10.1109\/12.990129","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:14:45Z","timestamp":1030220085000},"page":"313-326","source":"Crossref","is-referenced-by-count":3,"title":["Reducing memory latency via read-after-read memory dependence prediction"],"prefix":"10.1109","volume":"51","author":[{"given":"A.","family":"Moshovos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.S.","family":"Sohi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Fast Address Calculation","volume-title":"Proc. 22nd Int\u2019l Symp. Computer Architecture","author":"Austin","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476815"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765939"},{"key":"ref5","article-title":"Design and Evaluation of a Multiscalar Processor","volume-title":"Univ. Wisconsin-Madison","author":"Breach","year":"1998"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765940"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742776"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1147\/rd.374.0547"},{"issue":"nology","key":"ref10","article-title":"Speculative Execution Based on Value Prediction","author":"Gabbay","year":"1996"},{"article-title":"Hardware Support for Hiding Cache Latency","year":"1991","author":"Golden","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742783"},{"volume-title":"MIPS R2000\/R3000 RISC Architecture","year":"1987","author":"Kane","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/237721.237780"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263631"},{"key":"ref16","article-title":"Value Locality and Speculative Execution","volume-title":"Carnegie Mellon Univ.","author":"Lipasti","year":"1997"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566464"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"article-title":"Combining Branch Predictors","year":"1993","author":"McFarling","key":"ref19"},{"key":"ref20","article-title":"Memory Dependence Prediction","volume-title":"Univ. of Wisconsin-Madison","author":"Moshovos","year":"1998"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264189"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645814"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/2.675634"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742775"},{"article-title":"Profile Guided Load Marking for Memory Renaming","year":"1998","author":"Reinman","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645805"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645815"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742782"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645812"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/12276.13338"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/242694.242708"},{"article-title":"Increasing Cache Port Efficiency for Dynamic Superscalar Processors","volume-title":"Proc. 23rd Int\u2019l Symp. Computer Architecture","author":"Wilson","key":"ref32"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/xplorestaging.ieee.org\/ielx5\/12\/21340\/00990129.pdf?arnumber=990129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:36:04Z","timestamp":1742016964000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/ieeexplore.ieee.org\/document\/990129\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,3]]},"references-count":32,"journal-issue":{"issue":"3"},"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/12.990129","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2002,3]]}}}