{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:33:15Z","timestamp":1762032795463},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1109\/dsd.2008.67","type":"proceedings-article","created":{"date-parts":[[2008,11,11]],"date-time":"2008-11-11T18:55:15Z","timestamp":1226429715000},"page":"584-591","source":"Crossref","is-referenced-by-count":10,"title":["A New Array Fabric for Coarse-Grained Reconfigurable Architecture"],"prefix":"10.1109","author":[{"given":"Yoonjin","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rabi N.","family":"Mahapatra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"13"},{"year":"0","key":"14"},{"year":"0","journal-title":"Taiwan Semiconductor MC","key":"11"},{"year":"0","key":"12"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/ISVLSI.2003.1183360"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/12.859540"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/DATE.2001.915091"},{"year":"0","key":"10"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/IPDPS.2004.1303136"},{"key":"6","article-title":"energy-aware interconnect-exploration of coarse-grained reconflgurable processors","author":"lambrechts","year":"2005","journal-title":"Proc of Workshop on Application Specific Processors"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/ASPDAC.2000.835089"},{"key":"4","article-title":"analysis of the performance of coarse-grain reconfigurable architectures with different processing element configurations","author":"bansal","year":"2003","journal-title":"Proc of Workshop on Application Specific Processors"},{"year":"2002","author":"lee","article-title":"mapping loops on coarse-grained reconflgurable architectures using memory operation sharing","key":"9"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1007\/978-3-540-45234-8_23"}],"event":{"name":"2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools","start":{"date-parts":[[2008,9,3]]},"location":"Parma, Italy","end":{"date-parts":[[2008,9,5]]}},"container-title":["2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/xplorestaging.ieee.org\/ielx5\/4669199\/4669200\/04669288.pdf?arnumber=4669288","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T16:27:11Z","timestamp":1489681631000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/ieeexplore.ieee.org\/document\/4669288\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"references-count":14,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/dsd.2008.67","relation":{},"subject":[],"published":{"date-parts":[[2008]]}}}