{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T05:26:59Z","timestamp":1769923619840,"version":"3.49.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/iscas.2013.6572155","type":"proceedings-article","created":{"date-parts":[[2013,8,14]],"date-time":"2013-08-14T15:40:23Z","timestamp":1376494823000},"page":"1552-1555","source":"Crossref","is-referenced-by-count":5,"title":["Optimized algorithms for binary BCH codes"],"prefix":"10.1109","author":[{"family":"Min Yin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Menwang Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Bo Yi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.1997.613165"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693394"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378072"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/92.953498"},{"key":"2","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1109\/SIPS.2006.352599","article-title":"Low-power high-throughput bch error correction vlsi design for multi-level cell nand flash memories","author":"liu","year":"2006","journal-title":"Signal Processing Systems Design and Implementation 2006 SIPS '06 IEEE Workshop on"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1109\/ICASSP.2004.1327050","article-title":"Area efficient parallel decoder architecture for long bch codes","volume":"5","author":"chen","year":"2004","journal-title":"Acoustics Speech and Signal Processing 2004 Proceedings (ICASSP '04) IEEE International Conference on"},{"key":"10","author":"lin","year":"2004","journal-title":"Error Control Coding"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938160"},{"key":"6","first-page":"1003","article-title":"Low-complexity architecture of rs decoder for cmmb system","author":"guo","year":"2009","journal-title":"ASIC 2009 ASICON '09 IEEE 8th International Conference on"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.163"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1971.1054655"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/SECON.1995.513059"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSIT.2010.5564592"}],"event":{"name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Beijing","start":{"date-parts":[[2013,5,19]]},"end":{"date-parts":[[2013,5,23]]}},"container-title":["2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/xplorestaging.ieee.org\/ielx7\/6560459\/6571764\/06572155.pdf?arnumber=6572155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,21]],"date-time":"2019-07-21T00:11:15Z","timestamp":1563667875000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/http\/ieeexplore.ieee.org\/document\/6572155\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":13,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/iscas.2013.6572155","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}