{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:18:08Z","timestamp":1767705488743,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":55,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,9,19]],"date-time":"2012-09-19T00:00:00Z","timestamp":1348012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,9,19]]},"DOI":"10.1145\/2370816.2370868","type":"proceedings-article","created":{"date-parts":[[2012,9,25]],"date-time":"2012-09-25T23:48:43Z","timestamp":1348616923000},"page":"355-366","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":86,"title":["The evicted-address filter"],"prefix":"10.1145","author":[{"given":"Vivek","family":"Seshadri","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kozuch","sequence":"additional","affiliation":[{"name":"Intel Labs Pittsburgh, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Todd C.","family":"Mowry","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"AMD Phenom II key architectural features. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/iQBfK.  AMD Phenom II key architectural features. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/iQBfK."},{"key":"e_1_3_2_1_2_1","unstructured":"Intel next generation microarchitecture. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/3eskx.  Intel next generation microarchitecture. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/3eskx."},{"key":"e_1_3_2_1_3_1","unstructured":"Oracle SPARC T4. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/KZSnc.  Oracle SPARC T4. https:\/\/2.zoppoz.workers.dev:443\/http\/goo.gl\/KZSnc."},{"key":"e_1_3_2_1_4_1","unstructured":"Wind River Simics. www.windriver.com\/producs\/simics.  Wind River Simics. www.windriver.com\/producs\/simics."},{"key":"e_1_3_2_1_5_1","volume-title":"FAST","author":"Bansal S.","year":"2004","unstructured":"S. Bansal and D. S. Modha . CAR: Clock with adaptive replacement . In FAST , 2004 . S. Bansal and D. S. Modha. CAR: Clock with adaptive replacement. In FAST, 2004."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1274971.1275005"},{"key":"e_1_3_2_1_8_1","volume-title":"GLOBECOM","author":"Chen Y.","year":"2007","unstructured":"Y. Chen , A. Kumar , and J. Xu . A new design of Bloom Vlter for packet inspection speedup . In GLOBECOM , 2007 . Y. Chen, A. Kumar, and J. Xu. A new design of Bloom Vlter for packet inspection speedup. In GLOBECOM, 2007."},{"key":"e_1_3_2_1_9_1","volume-title":"MICRO","author":"Collins J.","year":"1999","unstructured":"J. Collins and D. M. Tullsen . Hardware identiVcation of cache conflict misses . In MICRO , 1999 . J. Collins and D. M. Tullsen. Hardware identiVcation of cache conflict misses. In MICRO, 1999."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2003.09.005"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1811039.1811056"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339660"},{"volume-title":"Intel 64 and IA-32 architectures software developer's manuals","year":"2011","key":"e_1_3_2_1_14_1","unstructured":"Intel. Intel 64 and IA-32 architectures software developer's manuals , 2011 . Intel. Intel 64 and IA-32 architectures software developer's manuals, 2011."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/511399.511340"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.817393"},{"key":"e_1_3_2_1_20_1","volume-title":"VLDB","author":"Johnson T.","year":"1994","unstructured":"T. Johnson and D. Shasha . 2Q: A low overhead high performance buffer management replacement algorithm . In VLDB , 1994 . T. Johnson and D. Shasha. 2Q: A low overhead high performance buffer management replacement algorithm. In VLDB, 1994."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.15"},{"key":"e_1_3_2_1_25_1","volume-title":"HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M. Harchol-Balter . ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers . In HPCA , 2010 . Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In HPCA, 2010."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"e_1_3_2_1_28_1","volume-title":"ISPASS","author":"Luo K.","year":"2001","unstructured":"K. Luo , J. Gummaraju , and M. Franklin . Balancing thoughput and fairness in SMT processors . In ISPASS , 2001 . K. Luo, J. Gummaraju, and M. Franklin. Balancing thoughput and fairness in SMT processors. In ISPASS, 2001."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594330"},{"key":"e_1_3_2_1_30_1","volume-title":"FAST","author":"Megiddo N.","year":"2003","unstructured":"N. Megiddo and D. S. Modha . ARC: A self-tuning, low overhead replacement cache . In FAST , 2003 . N. Megiddo and D. S. Modha. ARC: A self-tuning, low overhead replacement cache. In FAST, 2003."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/170035.170081"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514219"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74309-5_11"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.52"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.14"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.641938"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.537156"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669178"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.2010.5713184"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165152"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/635506.605403"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.165388"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.5555\/874076.876484"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225177"},{"key":"e_1_3_2_1_54_1","volume-title":"PACT","author":"Wang Z.","year":"2002","unstructured":"Z. Wang , K. S. McKinley , A. L. Rosenberg , and C. C. Weems . Using the compiler to improve cache replacement decisions . In PACT , 2002 . Z. Wang, K. S. McKinley, A. L. Rosenberg, and C. C. Weems. Using the compiler to improve cache replacement decisions. In PACT, 2002."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555778"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.31"}],"event":{"name":"PACT '12: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"],"location":"Minneapolis Minnesota USA","acronym":"PACT '12"},"container-title":["Proceedings of the 21st international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/2370816.2370868","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/2370816.2370868","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:34:17Z","timestamp":1750239257000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/2370816.2370868"}},"subtitle":["a unified mechanism to address both cache pollution and thrashing"],"short-title":[],"issued":{"date-parts":[[2012,9,19]]},"references-count":55,"alternative-id":["10.1145\/2370816.2370868","10.1145\/2370816"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/2370816.2370868","relation":{},"subject":[],"published":{"date-parts":[[2012,9,19]]},"assertion":[{"value":"2012-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}