{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:40:02Z","timestamp":1750236002701,"version":"3.41.0"},"reference-count":54,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[1996,12,1]],"date-time":"1996-12-01T00:00:00Z","timestamp":849398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[1996,12]]},"DOI":"10.1145\/242223.242271","type":"journal-article","created":{"date-parts":[[2002,7,27]],"date-time":"2002-07-27T11:32:04Z","timestamp":1027769524000},"page":"671-678","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Strategic directions in computer architecture"],"prefix":"10.1145","volume":"28","author":[{"given":"Trevor","family":"Mudge","sequence":"first","affiliation":[{"name":"Univ. of Michigan, Ann Arbor"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[1996,12]]},"reference":[{"volume-title":"Computer Architecture. Jones and Bartlett","author":"FLYNN M. J.","unstructured":"FLYNN , M. J. 1995. Computer Architecture. Jones and Bartlett , Boston, MA .]] FLYNN, M. J. 1995. Computer Architecture. Jones and Bartlett, Boston, MA.]]","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"HENNESSY J.","year":"1996","unstructured":"HENNESSY , J. , AND PATTERSON , D. 1996 . Computer Architecture: A Quantitative Approach ( 2 nd ed.), Morgan-Kaufmann , San Mateo, CA .]] HENNESSY, J., AND PATTERSON, D. 1996. Computer Architecture: A Quantitative Approach (2nd ed.), Morgan-Kaufmann, San Mateo, CA.]]","edition":"2"},{"key":"e_1_2_1_3_1","series-title":"May 21","volume-title":"Sponsored by the Microelectronic Systems Architecture Program of the Division of Microelectronic Information Processing Systems at NSF","author":"NSF","unstructured":"NSF 1996. NSF Workshop on Critical Issues in Computer Architecture Research , Sponsored by the Microelectronic Systems Architecture Program of the Division of Microelectronic Information Processing Systems at NSF ( May 21 ). https:\/\/2.zoppoz.workers.dev:443\/http\/www.cise.nsf.gov\/mips\/MSAWorkshop96\/ index2.html]] NSF 1996. NSF Workshop on Critical Issues in Computer Architecture Research, Sponsored by the Microelectronic Systems Architecture Program of the Division of Microelectronic Information Processing Systems at NSF (May 21). https:\/\/2.zoppoz.workers.dev:443\/http\/www.cise.nsf.gov\/mips\/MSAWorkshop96\/ index2.html]]"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1147\/rd.82.0087"},{"volume-title":"Computing machine for the solution of large systems of linear equations. Internal Rep","author":"ATANASOFF J.V.","unstructured":"ATANASOFF , J.V. 1940. Computing machine for the solution of large systems of linear equations. Internal Rep ., Iowa State University , Ames .]] ATANASOFF, J.V. 1940. Computing machine for the solution of large systems of linear equations. Internal Rep., Iowa State University, Ames.]]","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","first-page":"310","volume-title":"Proceedings of the Fourth Conference on Architectural Support for Programming Languages and Operating Systems","author":"BHANDARKAR D.","year":"1991","unstructured":"BHANDARKAR , D. , AND CLARK , D. W. 1991 . Performance from architecture: Comparing a RISC and a CISC with similar hardware organizations . In Proceedings of the Fourth Conference on Architectural Support for Programming Languages and Operating Systems , ( Palo Alto, CA, April) IEEE\/ACM , 310 - 319 .]] 10.1145\/106972.107003 BHANDARKAR, D., AND CLARK, D. W. 1991. Performance from architecture: Comparing a RISC and a CISC with similar hardware organizations. In Proceedings of the Fourth Conference on Architectural Support for Programming Languages and Operating Systems, (Palo Alto, CA, April) IEEE\/ACM, 310-319.]] 10.1145\/106972.107003"},{"key":"e_1_2_1_8_1","first-page":"657","article-title":"A new architecture for mini-computers: The DEC PDP-11","author":"BELL G.","year":"1970","unstructured":"BELL , G. , CADY , R. , MCFARLAND , H. , DELAGI , B. , O'LAUGHLIN , J. , NOONAN , R. , AND WULF , W. 1970 . A new architecture for mini-computers: The DEC PDP-11 . In Proceedings of AFIPS SJCC , 657 - 675 .]] BELL, G., CADY, R., MCFARLAND, H., DELAGI, B., O'LAUGHLIN, J., NOONAN, R., AND WULF, W. 1970. A new architecture for mini-computers: The DEC PDP-11. In Proceedings of AFIPS SJCC, 657-675.]]","journal-title":"Proceedings of AFIPS SJCC"},{"volume-title":"Planning a Computer Systern: Project Stretch","author":"BUCHOLTZ W.","unstructured":"BUCHOLTZ , W. 1962. Planning a Computer Systern: Project Stretch . McGraw-Hill , New York .]] BUCHOLTZ, W. 1962. Planning a Computer Systern: Project Stretch. McGraw-Hill, New York.]]","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","volume-title":"J.","author":"BURKS A. W.","year":"1946","unstructured":"BURKS , A. W. , GOLDSTINE , H. H. , AND VON NEU- MANN , J. 1946 . Preliminary discussion of the logical design of an electronic computing instrument. Rep. to the US Army Ordnance Department , p. 1; also appears in Papers of John von Neumann, W. Aspray and A. Burks, Eds., MIT Press, Cambridge, MA, and Tomash Publishers, Los Angeles, 1987, 97-146.]] BURKS, A. W., GOLDSTINE, H. H., AND VON NEU- MANN, J. 1946. Preliminary discussion of the logical design of an electronic computing instrument. Rep. to the US Army Ordnance Department, p. 1; also appears in Papers of John von Neumann, W. Aspray and A. Burks, Eds., MIT Press, Cambridge, MA, and Tomash Publishers, Los Angeles, 1987, 97-146.]]"},{"key":"e_1_2_1_11_1","first-page":"97","volume-title":"Proceedings of the Seventh Annual Symposium on Computer Architecture","author":"DITZEL D. R.","year":"1980","unstructured":"DITZEL , D. R. , AND CLARK , D.W. 1980 . Retrospective on high-level language computer architecture . In Proceedings of the Seventh Annual Symposium on Computer Architecture ( La Baule, France, June) , 97 - 104 .]] 10.1145\/800053.801914 DITZEL, D. R., AND CLARK, D.W. 1980. Retrospective on high-level language computer architecture. In Proceedings of the Seventh Annual Symposium on Computer Architecture (La Baule, France, June), 97-104.]] 10.1145\/800053.801914"},{"key":"e_1_2_1_12_1","volume-title":"The Computer: From Pascal to von Neumann","author":"GOLDSTINE H. H.","year":"1972","unstructured":"GOLDSTINE , H. H. 1972 . The Computer: From Pascal to von Neumann . Princeton University Press , Princeton, NJ .]] GOLDSTINE, H. H. 1972. The Computer: From Pascal to von Neumann. Princeton University Press, Princeton, NJ.]]"},{"key":"e_1_2_1_13_1","first-page":"245","article-title":"Burroughs B6500-B7500 stack mechanism","author":"HAUCK E. A.","year":"1968","unstructured":"HAUCK , E. A. , AND DENT , B.A. 1968 . Burroughs B6500-B7500 stack mechanism . In Proceedings of AFIPS SJCC , 245 - 251 .]] HAUCK, E. A., AND DENT, B.A. 1968. Burroughs B6500-B7500 stack mechanism. In Proceedings of AFIPS SJCC, 245-251.]]","journal-title":"Proceedings of AFIPS SJCC"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/TC.1984.1676395"},{"unstructured":"MENABREA L.F. 1842. Sketch of The Analytical Engine Invented by Charles Babbage. Bibiotheque Universelle de Geneve (Oct.).]] MENABREA L.F. 1842. Sketch of The Analytical Engine Invented by Charles Babbage. Bibiotheque Universelle de Geneve (Oct.).]]","key":"e_1_2_1_15_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1145\/2465.214917"},{"key":"e_1_2_1_17_1","first-page":"33","volume-title":"Proceedings of the AFIPS Fall Joint Computer Conference 26","author":"THORNTON J. E.","year":"1964","unstructured":"THORNTON , J. E. 1964 . Parallel operation in Control Data 6600 . In Proceedings of the AFIPS Fall Joint Computer Conference 26 , part 2, 33 - 40 .]] THORNTON, J. E. 1964. Parallel operation in Control Data 6600. In Proceedings of the AFIPS Fall Joint Computer Conference 26, part 2, 33-40.]]"},{"volume-title":"The Dynamics of the Computer Industry: Modeling the Supply of Workstations and Their Components","author":"TOUMA W.R.","unstructured":"TOUMA , W.R. 1993. The Dynamics of the Computer Industry: Modeling the Supply of Workstations and Their Components . Kluwer Academic , Boston .]] TOUMA, W.R. 1993. The Dynamics of the Computer Industry: Modeling the Supply of Workstations and Their Components. Kluwer Academic, Boston.]]","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","volume-title":"Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), 98-109","author":"UPTON M.","year":"1994","unstructured":"UPTON , M. , HUFF , T. , MUDGE , T. , AND BROWN , R. 1994 . Resource allocation in a high clock rate microprocessor . In Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), 98-109 .]] 10.1145\/195473.195510 UPTON, M., HUFF, T., MUDGE, T., AND BROWN, R. 1994. Resource allocation in a high clock rate microprocessor. In Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), 98-109.]] 10.1145\/195473.195510"},{"volume-title":"Memoirs of a Computer Pioneer","author":"WILKES M. V.","unstructured":"WILKES , M. V. 1985. Memoirs of a Computer Pioneer . MIT Press , Cambridge, MA .]] WILKES, M. V. 1985. Memoirs of a Computer Pioneer. MIT Press, Cambridge, MA.]]","key":"e_1_2_1_20_1"},{"volume-title":"Computing Perspectives. Morgan-Kaufmann","author":"WILKES M. V.","unstructured":"WILKES , M. V. 1995. Computing Perspectives. Morgan-Kaufmann , San Francisco .]] WILKES, M. V. 1995. Computing Perspectives. Morgan-Kaufmann, San Francisco.]]","key":"e_1_2_1_21_1"},{"key":"e_1_2_1_22_1","first-page":"181","article-title":"Effective control for pipelined processors. In COMPCON, (San Francisco, March)","author":"DAVIDSON E. S.","year":"1975","unstructured":"DAVIDSON , E. S. , THOMAS , A. T. , SHAR , L. E. , AND PATEL , J. H. 1975 . Effective control for pipelined processors. In COMPCON, (San Francisco, March) , IEEE 181 - 184 .]] DAVIDSON, E. S., THOMAS, A. T., SHAR, L. E., AND PATEL, J. H. 1975. Effective control for pipelined processors. In COMPCON, (San Francisco, March), IEEE 181-184.]]","journal-title":"IEEE"},{"doi-asserted-by":"publisher","key":"e_1_2_1_23_1","DOI":"10.5555\/5910"},{"key":"e_1_2_1_24_1","first-page":"140","volume-title":"Proceedings of the Tenth Symposium on Computer Architecture","author":"FISHER A.","year":"1983","unstructured":"FISHER , g. A. 1983 . Very long instruction word architectures and ELI-512 . In Proceedings of the Tenth Symposium on Computer Architecture ( Stockholm, June) , 140 - 150 .]] 10.1145\/800046.801649 FISHER, g.A. 1983. Very long instruction word architectures and ELI-512. In Proceedings of the Tenth Symposium on Computer Architecture (Stockholm, June), 140-150.]] 10.1145\/800046.801649"},{"key":"e_1_2_1_25_1","volume-title":"Institution of Electrical Engineers Proceedings - E, Computers and Digital Techniques.]]","author":"GOLDEN M.","year":"1996","unstructured":"GOLDEN , M. , AND MUDGE , T. 1996 . A comparison of two common pipeline structures . In Institution of Electrical Engineers Proceedings - E, Computers and Digital Techniques.]] GOLDEN, M., AND MUDGE, T. 1996. A comparison of two common pipeline structures. In Institution of Electrical Engineers Proceedings - E, Computers and Digital Techniques.]]"},{"key":"e_1_2_1_26_1","first-page":"297","volume-title":"Proceedings of the Thirteenth Symposium on Computer Architecture","author":"PATT Y.","year":"1986","unstructured":"Hwu, W.-M., AND PATT , Y. 1986 . HPSm, a high performance restricted data flow architecture having minimum functionality . In Proceedings of the Thirteenth Symposium on Computer Architecture ( Tokyo, June) , 297 - 307 .]] Hwu, W.-M., AND PATT, Y. 1986. HPSm, a high performance restricted data flow architecture having minimum functionality. In Proceedings of the Thirteenth Symposium on Computer Architecture (Tokyo, June), 297-307.]]"},{"volume-title":"Superscalar Microprocessor Design","author":"JOHNSON M.","unstructured":"JOHNSON , M. 1990. Superscalar Microprocessor Design , Prentice-Hall , Englewood Cliffs, NJ .]] JOHNSON, M. 1990. Superscalar Microprocessor Design, Prentice-Hall, Englewood Cliffs, NJ.]]","key":"e_1_2_1_27_1"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the Third Conference on Architectural Support for Programming Languages and Operating Systems","author":"PPI N. P.","year":"1989","unstructured":"Jou PPI , N. P. , AND WALL , D.W. 1989 . Available instruction-level parallelism for superscalar and superpipelined processors . In Proceedings of the Third Conference on Architectural Support for Programming Languages and Operating Systems , ( Boston, April), IEEE\/ACM 272- 282.]] 10.1145\/70082.68207 JouPPI, N. P., AND WALL, D.W. 1989. Available instruction-level parallelism for superscalar and superpipelined processors. In Proceedings of the Third Conference on Architectural Support for Programming Languages and Operating Systems, (Boston, April), IEEE\/ACM 272- 282.]] 10.1145\/70082.68207"},{"volume-title":"The Architecture of Pipelined Computers","author":"KOGGE P. M.","unstructured":"KOGGE , P. M. 1981. The Architecture of Pipelined Computers . McGraw-Hill , New York .]] KOGGE, P. M. 1981. The Architecture of Pipelined Computers. McGraw-Hill, New York.]]","key":"e_1_2_1_29_1"},{"key":"e_1_2_1_30_1","first-page":"135","volume-title":"Proceedings of the Eighth Symposium on Computer Architecture","author":"SMITH J.E.","year":"1981","unstructured":"SMITH , J.E. 1981 . A study of branch prediction strategies . In Proceedings of the Eighth Symposium on Computer Architecture ( Minneapolis, May) , 135 - 148 .]] SMITH, J.E. 1981. A study of branch prediction strategies. In Proceedings of the Eighth Symposium on Computer Architecture (Minneapolis, May), 135-148.]]"},{"key":"e_1_2_1_31_1","doi-asserted-by":"crossref","first-page":"248","DOI":"10.1145\/143365.143534","volume-title":"Proceedings of the Fifth Conference on Architectural Support for Programming Languages and Operating Systems","author":"SMITH M. D.","year":"1992","unstructured":"SMITH , M. D. , HOROWITZ , M. , AND LAM , M. S. 1992 . Efficient superscalar performance through boosting . In Proceedings of the Fifth Conference on Architectural Support for Programming Languages and Operating Systems ( Boston, Oct.), IEEE\/ACM , 248 - 259 .]] 10.1145\/143365.143534 SMITH, M. D., HOROWITZ, M., AND LAM, M. S. 1992. Efficient superscalar performance through boosting. In Proceedings of the Fifth Conference on Architectural Support for Programming Languages and Operating Systems (Boston, Oct.), IEEE\/ACM, 248-259.]] 10.1145\/143365.143534"},{"doi-asserted-by":"publisher","key":"e_1_2_1_32_1","DOI":"10.1109\/T-C.1970.222795"},{"doi-asserted-by":"publisher","key":"e_1_2_1_33_1","DOI":"10.1147\/rd.111.0025"},{"doi-asserted-by":"publisher","key":"e_1_2_1_34_1","DOI":"10.1109\/40.342018"},{"doi-asserted-by":"publisher","key":"e_1_2_1_35_1","DOI":"10.1145\/6513.6514"},{"doi-asserted-by":"publisher","key":"e_1_2_1_36_1","DOI":"10.1109\/PROC.1972.8647"},{"doi-asserted-by":"publisher","key":"e_1_2_1_37_1","DOI":"10.1109\/5.48826"},{"key":"e_1_2_1_38_1","first-page":"108","volume-title":"Proceedings of the East Joint Computer Conference 16","author":"HOLLAND J.H.","year":"1959","unstructured":"HOLLAND , J.H. 1959 . A universal computer capable of executing an arbitrary number of subprograms simultaneously . In Proceedings of the East Joint Computer Conference 16 , 108 - 113 .]] HOLLAND, J.H. 1959. A universal computer capable of executing an arbitrary number of subprograms simultaneously. In Proceedings of the East Joint Computer Conference 16, 108-113.]]"},{"key":"e_1_2_1_39_1","first-page":"148","volume-title":"Proceedings of the Seventh International Symposium on Computer Architecture","author":"LENOSKI D.","year":"1990","unstructured":"LENOSKI , D. , LAUDON , J. , GHARACHORLOO , K. , GUPTA , A. , AND HENNESSY , J. L. 1990 . The Stanford DASH multiprocessor . In Proceedings of the Seventh International Symposium on Computer Architecture ( Seattle, June) , 148 - 159 .]] 10.1145\/325164.325132 LENOSKI, D., LAUDON, J., GHARACHORLOO, K., GUPTA, A., AND HENNESSY, J. L. 1990. The Stanford DASH multiprocessor. In Proceedings of the Seventh International Symposium on Computer Architecture (Seattle, June), 148-159.]] 10.1145\/325164.325132"},{"key":"e_1_2_1_40_1","first-page":"303","volume-title":"Proceedings of the 1988 International Conference of Parallel Processing","author":"LOVETT T.","year":"1988","unstructured":"LOVETT , T. , AND THAKKAR , S. 1988 . The Symmetry multiprocessor system . In Proceedings of the 1988 International Conference of Parallel Processing ( University Park, PA.) , 303 - 310 .]] LOVETT, T., AND THAKKAR, S. 1988. The Symmetry multiprocessor system. In Proceedings of the 1988 International Conference of Parallel Processing (University Park, PA.), 303-310.]]"},{"doi-asserted-by":"publisher","key":"e_1_2_1_41_1","DOI":"10.1145\/357114.357116"},{"doi-asserted-by":"publisher","key":"e_1_2_1_42_1","DOI":"10.1145\/2465.2467"},{"key":"e_1_2_1_43_1","first-page":"97","volume-title":"Proceedings of the Fall Joint Computer Conference","author":"SLOTNICK D. L.","year":"1962","unstructured":"SLOTNICK , D. L. , BORCK , W. C. , AND MCREYNOLDS , R.C. 1962 . The Solomon computer . In Proceedings of the Fall Joint Computer Conference ( Philadelphia, Dec.) , 97 - 107 .]] SLOTNICK, D. L., BORCK, W. C., AND MCREYNOLDS, R.C. 1962. The Solomon computer. In Proceedings of the Fall Joint Computer Conference (Philadelphia, Dec.), 97-107.]]"},{"key":"e_1_2_1_44_1","first-page":"637","volume-title":"Proceedings AFIPS National Computer Conference 46","author":"SWAN R. J.","year":"1977","unstructured":"SWAN , R. J. , FULLER , S. H. , AND SIEWIOREK , D. P. 1977 . Cm*--A modular, multi-microprocessor . In Proceedings AFIPS National Computer Conference 46 , 637 - 644 .]] SWAN, R. J., FULLER, S. H., AND SIEWIOREK, D. P. 1977. Cm*--A modular, multi-microprocessor. In Proceedings AFIPS National Computer Conference 46, 637-644.]]"},{"doi-asserted-by":"publisher","key":"e_1_2_1_45_1","DOI":"10.1109\/2.348002"},{"key":"e_1_2_1_46_1","first-page":"245","volume-title":"Proceedings of the Computer Performance Evaluation Users Group, 16th Meeting, NBS 500-65","author":"BUCHER I. V.","year":"1980","unstructured":"BUCHER , I. V. , AND HAYES , A.H. 1980 . I\/O performance measurement on Cray-1 and CDC 7000 computers . In Proceedings of the Computer Performance Evaluation Users Group, 16th Meeting, NBS 500-65 , 245 - 254 .]] BUCHER, I. V., AND HAYES, A.H. 1980. I\/O performance measurement on Cray-1 and CDC 7000 computers. In Proceedings of the Computer Performance Evaluation Users Group, 16th Meeting, NBS 500-65, 245-254.]]"},{"doi-asserted-by":"publisher","key":"e_1_2_1_47_1","DOI":"10.1145\/176979.176981"},{"volume-title":"Digital Magnetic Recording","author":"HOAGLAND A. S.","unstructured":"HOAGLAND , A. S. 1963. Digital Magnetic Recording , Wiley , New York .]] HOAGLAND, A. S. 1963. Digital Magnetic Recording, Wiley, New York.]]","key":"e_1_2_1_48_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_49_1","DOI":"10.1109\/5.219343"},{"doi-asserted-by":"publisher","key":"e_1_2_1_50_1","DOI":"10.1109\/12.543711"},{"doi-asserted-by":"publisher","key":"e_1_2_1_51_1","DOI":"10.1109\/TEC.1962.5219356"},{"key":"e_1_2_1_52_1","volume-title":"Proceedings of the Nineteenth Annual International Symposium on Computer Architecture, 181-190","author":"OLUKOTUN O. A.","year":"1992","unstructured":"OLUKOTUN , O. A. , MUDGE , T. N. , AND BROWN , R. B. 1992 . Performance optimization of pipelined primary caches . In Proceedings of the Nineteenth Annual International Symposium on Computer Architecture, 181-190 .]] 10.1145\/139669.139726 OLUKOTUN, O. A., MUDGE, T. N., AND BROWN, R. B. 1992. Performance optimization of pipelined primary caches. In Proceedings of the Nineteenth Annual International Symposium on Computer Architecture, 181-190.]] 10.1145\/139669.139726"},{"key":"e_1_2_1_54_1","volume-title":"Cache Design: A Performance-Directed Approach","author":"PRZYBYLSKI S.A.","year":"1990","unstructured":"PRZYBYLSKI , S.A. 1990 . Cache Design: A Performance-Directed Approach . Morgan-Kaufmann Publishers , San Mateo, CA .]] PRZYBYLSKI, S.A. 1990. Cache Design: A Performance-Directed Approach. Morgan-Kaufmann Publishers, San Mateo, CA.]]"},{"doi-asserted-by":"publisher","key":"e_1_2_1_55_1","DOI":"10.1145\/356887.356892"},{"doi-asserted-by":"publisher","key":"e_1_2_1_56_1","DOI":"10.1145\/3959.3961"}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/242223.242271","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/242223.242271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:57Z","timestamp":1750234737000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/242223.242271"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,12]]},"references-count":54,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1996,12]]}},"alternative-id":["10.1145\/242223.242271"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/242223.242271","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"type":"print","value":"0360-0300"},{"type":"electronic","value":"1557-7341"}],"subject":[],"published":{"date-parts":[[1996,12]]},"assertion":[{"value":"1996-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}