{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:18:46Z","timestamp":1750306726549,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":4,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,8,24]],"date-time":"2014-08-24T00:00:00Z","timestamp":1408838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"UK-India Education and Research Initiative","award":["UKUTP201100288"],"award-info":[{"award-number":["UKUTP201100288"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,8,24]]},"DOI":"10.1145\/2628071.2671424","type":"proceedings-article","created":{"date-parts":[[2015,1,12]],"date-time":"2015-01-12T20:42:45Z","timestamp":1421095365000},"page":"507-508","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Data Remapping for an Energy Efficient Burst Chop in DRAM Memory Systems"],"prefix":"10.1145","author":[{"given":"Sudharsan","family":"Jagathrakshakan","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Venkata Kalyan","family":"Tavva","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhu","family":"Mutyam","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,8,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"MICRON Calculating Memory System Power for DDR3L.  MICRON Calculating Memory System Power for DDR3L."},{"volume-title":"JEDEC Committee JC-42.3 Std. DDR4","year":"2012","key":"e_1_3_2_1_2_1","unstructured":"JESD79--4 , JEDEC Committee JC-42.3 Std. DDR4 . Sept. 2012 . JESD79--4, JEDEC Committee JC-42.3 Std. DDR4. Sept. 2012."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"}],"event":{"name":"PACT '14: International Conference on Parallel Architectures and Compilation","sponsor":["IFIP WG 10.3 IFIP WG 10.3","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"],"location":"Edmonton AB Canada","acronym":"PACT '14"},"container-title":["Proceedings of the 23rd international conference on Parallel architectures and compilation"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/2628071.2671424","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/2628071.2671424","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:38Z","timestamp":1750231178000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/2628071.2671424"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8,24]]},"references-count":4,"alternative-id":["10.1145\/2628071.2671424","10.1145\/2628071"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/2628071.2671424","relation":{},"subject":[],"published":{"date-parts":[[2014,8,24]]},"assertion":[{"value":"2014-08-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}