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Syst."],"published-print":{"date-parts":[[2016,7,26]]},"abstract":"<jats:p>Multicore processors are increasingly adopted in resource-constrained real-time embedded applications. In the development of such applications, efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and to reduce system stack usage. In this paper, we consider partitioned multi-processor scheduling on a multicore processor with either Fixed-Priority or Earliest Deadline First scheduling algorithms with PTS and address the design optimization problem of mapping tasks to processor cores and assignment of task priorities and preemption thresholds with the optimization objective of minimizing system stack usage. We present both optimal solution techniques based on Mixed Integer Linear Programming and efficient heuristic algorithms that can achieve high-quality results. We perform extensive performance evaluations using both synthetic tasksets and industrial case studies.<\/jats:p>","DOI":"10.1145\/2846096","type":"journal-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T14:30:58Z","timestamp":1463149858000},"page":"1-25","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling"],"prefix":"10.1145","volume":"21","author":[{"given":"Chao","family":"Wang","sequence":"first","affiliation":[{"name":"Zhejiang University, China, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chuansheng","family":"Dong","sequence":"additional","affiliation":[{"name":"McGill University, Canada, QC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haibo","family":"Zeng","sequence":"additional","affiliation":[{"name":"Virginia Tech, USA, Blacksburg, VA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zonghua","family":"Gu","sequence":"additional","affiliation":[{"name":"Zhejiang University, China, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2016,5,11]]},"reference":[{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1990.128747"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2006.41"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the International Conference on Design and Architectures for Signal and Image Processing.","author":"Baruah S.","unstructured":"S. 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