{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:48:28Z","timestamp":1759146508741,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[1999,6,1]],"date-time":"1999-06-01T00:00:00Z","timestamp":928195200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[1999,6]]},"DOI":"10.1145\/309847.310105","type":"proceedings-article","created":{"date-parts":[[2003,11,14]],"date-time":"2003-11-14T17:36:23Z","timestamp":1068831383000},"page":"951-957","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Behavioral synthesis of analog systems using two-layered design space exploration"],"prefix":"10.1145","author":[{"given":"Alex","family":"Doboli","sequence":"first","affiliation":[{"name":"Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian","family":"Nunez-Aldana","sequence":"additional","affiliation":[{"name":"Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagu","family":"Dhanwada","sequence":"additional","affiliation":[{"name":"Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sree","family":"Ganesan","sequence":"additional","affiliation":[{"name":"Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[{"name":"Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati, Cincinnati, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[1999,6]]},"reference":[{"key":"e_1_3_2_1_1_2","unstructured":"\"IEEE Standard VHDL Language Reference Manual (Integrated with VHDL- AMS changes)\" IEEE Std. 1076.1.  \"IEEE Standard VHDL Language Reference Manual (Integrated with VHDL- AMS changes)\" IEEE Std. 1076.1."},{"key":"e_1_3_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277052"},{"key":"e_1_3_2_1_3_2","unstructured":"R Campisi \"A CMOS Analog Cell Library for Analog Synthesis Systems\" Master of Science Thesis University of Cincinnati 1998.  R Campisi \"A CMOS Analog Cell Library for Analog Synthesis Systems\" Master of Science Thesis University of Cincinnati 1998."},{"key":"e_1_3_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240573"},{"key":"e_1_3_2_1_5_2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-8752-5","volume-title":"A Top-Down Constraint Driven Methodology for Analog Integrated Circuits","author":"H. Chang","year":"1997","unstructured":"H. Chang et al , \" A Top-Down Constraint Driven Methodology for Analog Integrated Circuits \", Kluwer Academic , 1997 . H. Chang et al, \"A Top-Down Constraint Driven Methodology for Analog Integrated Circuits\", Kluwer Academic, 1997."},{"key":"e_1_3_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.75012"},{"key":"e_1_3_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307517"},{"key":"e_1_3_2_1_8_2","volume-title":"IEEE\/VIUF BMAS'98","author":"Doboli A.","year":"1998","unstructured":"A. Doboli , R. Vemuri , \"The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems \", IEEE\/VIUF BMAS'98 , 1998 . A. Doboli, R. Vemuri, \"The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems\", IEEE\/VIUF BMAS'98, 1998."},{"key":"e_1_3_2_1_9_2","volume-title":"Technical Report, DDEL","author":"Doboli A.","year":"1998","unstructured":"A. Doboli , A. Nunez-Aldana , N. Dhanwada , R. Vemuri , \" VHIF - A Hierarchical Representation for Behavioral Synthesis of Analog Systems from VHDL-AMS\" , Technical Report, DDEL , University of Cincinnati , April 1998 . A. Doboli, A. Nunez-Aldana, N. Dhanwada, R. Vemuri, \"VHIF - A Hierarchical Representation for Behavioral Synthesis of Analog Systems from VHDL-AMS\", Technical Report, DDEL, University of Cincinnati, April 1998."},{"key":"e_1_3_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307518"},{"key":"e_1_3_2_1_11_2","doi-asserted-by":"publisher","DOI":"10.1007\/BF00713982"},{"key":"e_1_3_2_1_12_2","unstructured":"S. Franco \"Design with Operational Amplifiers and Analog Integrated Circuits\" McGraw Hill 1988.  S. Franco \"Design with Operational Amplifiers and Analog Integrated Circuits\" McGraw Hill 1988."},{"key":"e_1_3_2_1_13_2","doi-asserted-by":"crossref","unstructured":"M. Gen R. Cheng \"Genetic Algorithms and Engineering Design\" John Wiley & Sons 1997.   M. Gen R. Cheng \"Genetic Algorithms and Engineering Design\" John Wiley & Sons 1997.","DOI":"10.1002\/9780470172254"},{"key":"e_1_3_2_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.102664"},{"key":"e_1_3_2_1_15_2","volume-title":"Computer Science Press","author":"Horowitz E.","year":"1985","unstructured":"E. Horowitz , S. Sahni , \" Fundamentals of Computer Algorithms\" , Computer Science Press , 1985 . E. Horowitz, S. Sahni, \"Fundamentals of Computer Algorithms\", Computer Science Press, 1985."},{"key":"e_1_3_2_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/31.55038"},{"key":"e_1_3_2_1_17_2","volume-title":"1st Int'l Workshop on Design of Mixed-Mode Integrated Cilvuits and Applications","author":"Hershenson Mar","year":"1997","unstructured":"M.del Mar Hershenson , S. Boyd , T. Lee ,\" CMOS Operational Amplifier Design and Optimization via Geometric Programming\",P~vc. 1st Int'l Workshop on Design of Mixed-Mode Integrated Cilvuits and Applications , 1997 . M.del Mar Hershenson,S.Boyd,T.Lee,\"CMOS Operational Amplifier Design and Optimization via Geometric Programming\",P~vc. 1st Int'l Workshop on Design of Mixed-Mode Integrated Cilvuits and Applications, 1997."},{"key":"e_1_3_2_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307533"},{"key":"e_1_3_2_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.3185"},{"key":"e_1_3_2_1_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/196244.196258"}],"event":{"name":"DAC99: The 36th ACM\/IEEE-CAS\/EDAC Design Automation Conference","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CAS Circuits & Systems"],"location":"New Orleans Louisiana USA","acronym":"DAC99"},"container-title":["Proceedings of the 36th annual ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/309847.310105","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/309847.310105","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:04:35Z","timestamp":1750273475000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/309847.310105"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,6]]},"references-count":20,"alternative-id":["10.1145\/309847.310105","10.1145\/309847"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/309847.310105","relation":{},"subject":[],"published":{"date-parts":[[1999,6]]},"assertion":[{"value":"1999-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}