{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T15:57:37Z","timestamp":1776182257766,"version":"3.50.1"},"reference-count":70,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2020,12,6]],"date-time":"2020-12-06T00:00:00Z","timestamp":1607212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2021,11,30]]},"abstract":"<jats:p>Platforms combining Central Processing Systems (CPUs) with Field Programmable Gate Arrays (FPGAs) have become popular, as they promise high performance with energy efficiency. This is the result of the combination of FPGA accelerators tuned to the application, with the CPU providing the programming flexibility. Unfortunately, the security of these new platforms has received little attention: The classic software security assumption that hardware is immutable no longer holds. It is expected that attack surfaces will expand and threats will evolve, hence the trust models, and security solutions should be prepared. The attacker model should be enhanced and consider the following three basic entities as the source of threats: applications run by users, accelerators designed by third-party developers, and the cloud service providers enabling the computation on their platforms. In our work, we review current trust models and existing security assumptions and point out their shortcomings. We survey existing research that target secure remote FPGA configuration, the protection of intellectual property, and secure shared use of FPGAs. When combined, these are the foundations to build a solution for secure use of FPGAs in the cloud. In addition to analysing the existing research, we provide discussions on how to improve it and disclose various concerns that have not been addressed yet.<\/jats:p>","DOI":"10.1145\/3419100","type":"journal-article","created":{"date-parts":[[2020,12,6]],"date-time":"2020-12-06T22:23:20Z","timestamp":1607293400000},"page":"1-28","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["Trust in FPGA-accelerated Cloud Computing"],"prefix":"10.1145","volume":"53","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-0045-7794","authenticated-orcid":false,"given":"Furkan","family":"Turan","sequence":"first","affiliation":[{"name":"imec-COSIC, KU Leuven, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-0879-076X","authenticated-orcid":false,"given":"Ingrid","family":"Verbauwhede","sequence":"additional","affiliation":[{"name":"imec-COSIC, KU Leuven, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2020,12,6]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"2013. Xilinx Announces Full Production of Its Entire Zynq-7000 All Programmable SoC Family. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2013\/xilinx-announces-full-production-of-its-entire-zynq-7000-all-programmable-soc- family.html.  2013. Xilinx Announces Full Production of Its Entire Zynq-7000 All Programmable SoC Family. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2013\/xilinx-announces-full-production-of-its-entire-zynq-7000-all-programmable-soc- family.html."},{"key":"e_1_2_1_2_1","volume-title":"IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)","year":"2014","unstructured":"2015. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) . IEEE Std 1735- 2014 (Incorporates IEEE Std 1735-2014\/Cor 1-2015) (September 2015). DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/IEEESTD.2015.7274481 10.1109\/IEEESTD.2015.7274481 2015. IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP). IEEE Std 1735-2014 (Incorporates IEEE Std 1735-2014\/Cor 1-2015) (September 2015). DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/IEEESTD.2015.7274481"},{"key":"e_1_2_1_3_1","unstructured":"2015. Intel Acquisition of Altera. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/newsroom.intel.com\/press-kits\/intel-acquisition-of- altera\/.  2015. Intel Acquisition of Altera. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/newsroom.intel.com\/press-kits\/intel-acquisition-of- altera\/."},{"key":"e_1_2_1_4_1","unstructured":"2016. Developer Preview\u2014EC2 Instances (F1) with Programmable Hardware. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/aws.amazon.com\/blogs\/aws\/developer-preview-ec2-instances-f1-with-programmable-hardware\/.  2016. Developer Preview\u2014EC2 Instances (F1) with Programmable Hardware. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/aws.amazon.com\/blogs\/aws\/developer-preview-ec2-instances-f1-with-programmable-hardware\/."},{"key":"e_1_2_1_5_1","unstructured":"2017. Baidu Deploys Xilinx FPGAs in New Public Cloud Acceleration Services. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/baidu-deploys-xilinx-fpgas-in-new-public-cloud-acceleration-services.html.  2017. Baidu Deploys Xilinx FPGAs in New Public Cloud Acceleration Services. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/baidu-deploys-xilinx-fpgas-in-new-public-cloud-acceleration-services.html."},{"key":"e_1_2_1_6_1","unstructured":"2017. Intel FPGAs Power Acceleration-as-a-Service for Alibaba Cloud. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/newsroom.intel.com\/news\/intel-fpgas-power-acceleration-as-a-service-alibaba-cloud\/.  2017. Intel FPGAs Power Acceleration-as-a-Service for Alibaba Cloud. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/newsroom.intel.com\/news\/intel-fpgas-power-acceleration-as-a-service-alibaba-cloud\/."},{"key":"e_1_2_1_7_1","unstructured":"2017. Xilinx Powers Huawei FPGA Accelerated Cloud Server. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/xilinx-powers-huawei-fpga-accelerated-cloud-server.html.  2017. Xilinx Powers Huawei FPGA Accelerated Cloud Server. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/xilinx-powers-huawei-fpga-accelerated-cloud-server.html."},{"key":"e_1_2_1_8_1","unstructured":"2017. Xilinx Selected by Alibaba Cloud for Next-Gen FPGA Cloud Acceleration. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/xilinx-selected-by-alibaba-cloud-for-next-gen-fpga-cloud-acceleration.html.  2017. Xilinx Selected by Alibaba Cloud for Next-Gen FPGA Cloud Acceleration. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/news\/press\/2017\/xilinx-selected-by-alibaba-cloud-for-next-gen-fpga-cloud-acceleration.html."},{"key":"e_1_2_1_9_1","unstructured":"2018. Tencent Cloud\u2014Instance Type FPGA FX2. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/intl.cloud.tencent.com\/document\/product\/213\/11518#FX2.  2018. Tencent Cloud\u2014Instance Type FPGA FX2. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/intl.cloud.tencent.com\/document\/product\/213\/11518#FX2."},{"key":"e_1_2_1_10_1","unstructured":"2018. Twitch Chooses Xilinx to Enable Its Broadcast-quality Livestream of eSports. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/forums.xilinx.com\/t5\/Xilinx-Xclusive-Blog\/Live-from-XDF-Twitch-Chooses-Xilinx-to-Enable-its-Broadcast\/ba-p\/894711.  2018. Twitch Chooses Xilinx to Enable Its Broadcast-quality Livestream of eSports. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/forums.xilinx.com\/t5\/Xilinx-Xclusive-Blog\/Live-from-XDF-Twitch-Chooses-Xilinx-to-Enable-its-Broadcast\/ba-p\/894711."},{"key":"e_1_2_1_11_1","unstructured":"2019. Confidential Computing Consortium. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/confidentialcomputing.io\/.  2019. Confidential Computing Consortium. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/confidentialcomputing.io\/."},{"key":"e_1_2_1_12_1","unstructured":"2019. Open Programmable Acceleration Engine. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/opae.github.io\/1.0.2\/index.html.  2019. Open Programmable Acceleration Engine. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/opae.github.io\/1.0.2\/index.html."},{"key":"e_1_2_1_13_1","unstructured":"2019. What Are Field-programmable Gate Arrays (FPGA) and How to Deploy. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/docs.microsoft.com\/en-us\/azure\/machine-learning\/service\/how-to-deploy-fpga-web-service.  2019. What Are Field-programmable Gate Arrays (FPGA) and How to Deploy. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/docs.microsoft.com\/en-us\/azure\/machine-learning\/service\/how-to-deploy-fpga-web-service."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2017.13"},{"key":"e_1_2_1_15_1","unstructured":"ARM. 2013. AMBA AXI and ACE Protocol Specification. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/developer.arm.com\/documentation\/ihi0022\/e\/.  ARM. 2013. AMBA AXI and ACE Protocol Specification. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/developer.arm.com\/documentation\/ihi0022\/e\/."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2661582"},{"key":"e_1_2_1_17_1","volume-title":"Debapriya Basu Roy, and Debdeep Mukhopadhyay","author":"Bag Arnab","year":"2018","unstructured":"Arnab Bag , Sikhar Patranabis , Debapriya Basu Roy, and Debdeep Mukhopadhyay . 2018 . Cryptographically secure multi-tenant provisioning of FPGAs. CoRR abs\/1802.04136 (2018). Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/arxiv.org\/abs\/1802.04136. Arnab Bag, Sikhar Patranabis, Debapriya Basu Roy, and Debdeep Mukhopadhyay. 2018. Cryptographically secure multi-tenant provisioning of FPGAs. CoRR abs\/1802.04136 (2018). Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/arxiv.org\/abs\/1802.04136."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1314333.1314337"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1030083.1030103"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9083-9"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195647"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597929"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3134040"},{"key":"e_1_2_1_24_1","unstructured":"Eric Chung and Jeremy Fowers. 2017. Accelerating Persistent Neural Networks at Datacenter Scale. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.hotchips.org\/archives\/2010s\/hc29\/.  Eric Chung and Jeremy Fowers. 2017. Accelerating Persistent Neural Networks at Datacenter Scale. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.hotchips.org\/archives\/2010s\/hc29\/."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.44"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339241"},{"key":"e_1_2_1_27_1","unstructured":"Saar Drimer Tim G\u00fcneysu Markus G. Kuhn and Christof Paar. 2008. Protecting Multiple Cores in a Single FPGA Design. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/http\/www.cl.cam.ac.uk\/sd410\/.  Saar Drimer Tim G\u00fcneysu Markus G. Kuhn and Christof Paar. 2008. Protecting Multiple Cores in a Single FPGA Design. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/http\/www.cl.cam.ac.uk\/sd410\/."},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications (ARC\u201909)","author":"Drimer Saar","unstructured":"Saar Drimer and Markus G. Kuhn . 2009. A protocol for secure remote updates of FPGA configurations . In Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications (ARC\u201909) . 50--61. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/978-3-642-00641-8_8 10.1007\/978-3-642-00641-8_8 Saar Drimer and Markus G. Kuhn. 2009. A protocol for secure remote updates of FPGA configurations. In Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications (ARC\u201909). 50--61. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/978-3-642-00641-8_8"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339242"},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the 19th Annual Network and Distributed System Security Symposium (NDSS\u201912)","author":"Eldefrawy Karim","year":"2012","unstructured":"Karim Eldefrawy , Gene Tsudik , Aur\u00e9lien Francillon , and Daniele Perito . 2012 . SMART: Secure and minimal architecture for (establishing dynamic) root of trust . In Proceedings of the 19th Annual Network and Distributed System Security Symposium (NDSS\u201912) . Karim Eldefrawy, Gene Tsudik, Aur\u00e9lien Francillon, and Daniele Perito. 2012. SMART: Secure and minimal architecture for (establishing dynamic) root of trust. In Proceedings of the 19th Annual Network and Distributed System Security Symposium (NDSS\u201912)."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3196494.3196518"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2007.4439246"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2741464"},{"key":"e_1_2_1_34_1","volume-title":"Handbook of FPGA Design Security","author":"Huffmire Ted","unstructured":"Ted Huffmire , Cynthia Irvine , Thuy D. Nguyen , Timothy Levin , Ryan Kastner , and Timothy Sherwood . 2010. Handbook of FPGA Design Security . Springer Science 8 Business Media. Ted Huffmire, Cynthia Irvine, Thuy D. Nguyen, Timothy Levin, Ryan Kastner, and Timothy Sherwood. 2010. Handbook of FPGA Design Security. Springer Science 8 Business Media."},{"key":"e_1_2_1_35_1","unstructured":"Intel. 2020. Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Datasheet. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ds\/ds-pac-a10.pdf.  Intel. 2020. Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GX FPGA Datasheet. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ds\/ds-pac-a10.pdf."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.48"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2815631"},{"key":"e_1_2_1_38_1","unstructured":"Chenglu Jin Vasudev Gohil Ramesh Karri and Jeyavijayan Rajendran. 2020. Security of cloud FPGAs: A survey. arXiv:2005.04867. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/arxiv.org\/abs\/2005.04867.  Chenglu Jin Vasudev Gohil Ramesh Karri and Jeyavijayan Rajendran. 2020. Security of cloud FPGAs: A survey. arXiv:2005.04867. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/arxiv.org\/abs\/2005.04867."},{"key":"e_1_2_1_39_1","unstructured":"Simon Johnson. 2019. Systex 2019 Keynote Talk - Scaling Towards Confidential Computing. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/systex.ibr.cs.tu-bs.de\/systex19\/slides\/systex19-keynote-simon.pdf.  Simon Johnson. 2019. Systex 2019 Keynote Talk - Scaling Towards Confidential Computing. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/systex.ibr.cs.tu-bs.de\/systex19\/slides\/systex19-keynote-simon.pdf."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.61"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-17227-5_11"},{"key":"e_1_2_1_42_1","article-title":"FPGAs and the cloud--An endless tale of virtualization, elasticity and efficiency","volume":"11","author":"Knodel Oliver","year":"2018","unstructured":"Oliver Knodel , Paul R. Genssler , Fredo Erxleben , and Rainer G. Spallek . 2018 . FPGAs and the cloud--An endless tale of virtualization, elasticity and efficiency . Int. J. Adv. Syst. Meas. 11 , 3 (2018). Oliver Knodel, Paul R. Genssler, Fredo Erxleben, and Rainer G. Spallek. 2018. FPGAs and the cloud--An endless tale of virtualization, elasticity and efficiency. Int. J. Adv. Syst. Meas. 11, 3 (2018).","journal-title":"Int. J. Adv. Syst. Meas."},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i3.44-68"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i3.573-595"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596540"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2647955"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2169667"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375390"},{"key":"e_1_2_1_49_1","volume-title":"Proceedings of the 2nd Workshop on Hardware and Architectural Support for Security and Privacy (HASP\u201913)","author":"McKeen Frank","unstructured":"Frank McKeen , Ilya Alexandrovich , Alex Berenzon , Carlos V. Rozas , Hisham Shafi , Vedvyas Shanbhogue , and Uday R. Savagaonkar . 2013. Innovative instructions and software model for isolated execution . In Proceedings of the 2nd Workshop on Hardware and Architectural Support for Security and Privacy (HASP\u201913) . 10. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/2487726.2488368 10.1145\/2487726.2488368 Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos V. Rozas, Hisham Shafi, Vedvyas Shanbhogue, and Uday R. Savagaonkar. 2013. Innovative instructions and software model for isolated execution. In Proceedings of the 2nd Workshop on Hardware and Architectural Support for Security and Privacy (HASP\u201913). 10. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/2487726.2488368"},{"key":"e_1_2_1_50_1","volume-title":"Vanstone","author":"Menezes Alfred","year":"1996","unstructured":"Alfred Menezes , Paul C. van Oorschot , and Scott A . Vanstone . 1996 . Handbook of Applied Cryptography. CRC Press . Alfred Menezes, Paul C. van Oorschot, and Scott A. Vanstone. 1996. Handbook of Applied Cryptography. CRC Press."},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2046707.2046722"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00016"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.9"},{"key":"e_1_2_1_55_1","volume-title":"Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA\u201919)","author":"Roy Sujoy Sinha","year":"2019","unstructured":"Sujoy Sinha Roy , Furkan Turan , Kimmo J\u00e4rvinen , Frederik Vercauteren , and Ingrid Verbauwhede . 2019 . FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data . In Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA\u201919) . 387--398. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HPCA.2019.00052 10.1109\/HPCA.2019.00052 Sujoy Sinha Roy, Furkan Turan, Kimmo J\u00e4rvinen, Frederik Vercauteren, and Ingrid Verbauwhede. 2019. FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data. In Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA\u201919). 387--398. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HPCA.2019.00052"},{"key":"e_1_2_1_56_1","article-title":"A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH","volume":"7","author":"Kwok-Hay So Hayden","year":"2008","unstructured":"Hayden Kwok-Hay So and Robert W. Brodersen . 2008 . A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH . ACM Trans. Embedd. Comput. Syst. 7 , 2 (2008), 14:1--14:28. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/1331331.1331338 10.1145\/1331331.1331338 Hayden Kwok-Hay So and Robert W. Brodersen. 2008. A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Trans. Embedd. Comput. Syst. 7, 2 (2008), 14:1--14:28. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/1331331.1331338","journal-title":"ACM Trans. Embedd. Comput. Syst."},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-016-0132-7"},{"key":"e_1_2_1_59_1","unstructured":"SymbiFlow2019. 2018. SymbiFlow\u2014Open Source FPGA Tooling for Rapid Innivation. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/symbiflow.github.io\/.  SymbiFlow2019. 2018. SymbiFlow\u2014Open Source FPGA Tooling for Rapid Innivation. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/symbiflow.github.io\/."},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375322"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2331672"},{"key":"e_1_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00031"},{"key":"e_1_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2013.6732330"},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714775"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_84"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04444-1_22"},{"key":"e_1_2_1_68_1","unstructured":"Zane Weissman Thore Tiemann Daniel Moghimi Evan Custodio Thomas Eisenbarth and Berk Sunar. 2019. JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arxiv:cs.CR\/1912.11523. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/http\/arxiv.org\/abs\/cs.CR\/1912.11523.  Zane Weissman Thore Tiemann Daniel Moghimi Evan Custodio Thomas Eisenbarth and Berk Sunar. 2019. JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arxiv:cs.CR\/1912.11523. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/http\/arxiv.org\/abs\/cs.CR\/1912.11523."},{"key":"e_1_2_1_69_1","unstructured":"Xilinx. 2020. XAPP1283\u2014Internal Programming of BBRAM and eFUSEs. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1283-internalprogramming-bbram-efuses.pdf.  Xilinx. 2020. XAPP1283\u2014Internal Programming of BBRAM and eFUSEs. Retrieved from https:\/\/2.zoppoz.workers.dev:443\/https\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1283-internalprogramming-bbram-efuses.pdf."},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124743"},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2355043"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00049"}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3419100","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/3419100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:32:05Z","timestamp":1750195925000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3419100"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12,6]]},"references-count":70,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2021,11,30]]}},"alternative-id":["10.1145\/3419100"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/3419100","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"value":"0360-0300","type":"print"},{"value":"1557-7341","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,12,6]]},"assertion":[{"value":"2020-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2020-12-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}