{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,11]],"date-time":"2026-07-11T02:48:34Z","timestamp":1783738114067,"version":"3.55.0"},"reference-count":148,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"EU Horizon 2020 program as E2Data","award":["780245"],"award-info":[{"award-number":["780245"]}]},{"name":"DFG","award":["MA4662-5"],"award-info":[{"award-number":["MA4662-5"]}]},{"name":"German Ministry for Education and Research as BIFOLD-BBDC","award":["01IS18025A"],"award-info":[{"award-number":["01IS18025A"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2023,1,31]]},"abstract":"<jats:p>\n            Due to their high computational power and internal memory bandwidth,\n            <jats:bold>graphic processing units (GPUs)<\/jats:bold>\n            have been extensively studied by the database systems research community. A heterogeneous query processing system that employs CPUs and GPUs at the same time has to solve many challenges, including how to distribute the workload on processors with different capabilities; how to overcome the data transfer bottleneck; and how to support implementations for multiple processors efficiently. In this survey we devise a classification scheme to categorize techniques developed to address these challenges. Based on this scheme, we categorize query processing systems on heterogeneous CPU\/GPU systems and identify open research problems.\n          <\/jats:p>","DOI":"10.1145\/3485126","type":"journal-article","created":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T15:47:38Z","timestamp":1642434458000},"page":"1-38","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":50,"title":["Query Processing on Heterogeneous CPU\/GPU Systems"],"prefix":"10.1145","volume":"55","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-6001-4442","authenticated-orcid":false,"given":"Viktor","family":"Rosenfeld","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Berlin, Berlin, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sebastian","family":"Bre\u00df","sequence":"additional","affiliation":[{"name":"Snowflake Inc., Berlin, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Volker","family":"Markl","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Berlin, Berlin, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,1,17]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/872757.872855"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385658.3385668"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142548"},{"key":"e_1_3_2_5_2","unstructured":"Advanced Micro Devices. 2021. More About How ROCm Uses PCIe Atomics. https:\/\/2.zoppoz.workers.dev:443\/https\/rocmdocs.amd.com\/en\/latest\/Installation_Guide\/More-about-how-ROCm-uses-PCIe-Atomics.html."},{"key":"e_1_3_2_6_2","first-page":"57","volume-title":"Proc. of ADMS\/IMDM@VLDB\u201917","author":"Agbaria Adnan","year":"2017","unstructured":"Adnan Agbaria, David Minor, Natan Peterfreund, Eyal Rozenberg, and Ofer Rosenberg. 2017. Overtaking CPU DBMSes with a GPU in whole-query analytic processing with parallelism-friendly execution plan optimization. In Proc. of ADMS\/IMDM@VLDB\u201917. Springer International Publishing, 57\u201378. https:\/\/2.zoppoz.workers.dev:443\/https\/link.springer.com\/chapter\/10.1007\/978-3-319-56111-0_4."},{"key":"e_1_3_2_7_2","first-page":"1","volume-title":"Proc. of IEEE HCS 21","author":"Ajanovic Jasmin","year":"2009","unstructured":"Jasmin Ajanovic. 2009. PCI express 3.0 overview. In Proc. of IEEE HCS 21. 1\u201361. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2009.7478337"},{"key":"e_1_3_2_8_2","volume-title":"Proc. of CIDR\u201917","author":"Appuswamy Raja","year":"2017","unstructured":"Raja Appuswamy, Manos Karpathiotakis, Danica Porobic, and Anastasia Ailamaki. 2017. The case for heterogeneous HTAP. In Proc. of CIDR\u201917. https:\/\/2.zoppoz.workers.dev:443\/http\/infoscience.epfl.ch\/record\/224447."},{"key":"e_1_3_2_9_2","first-page":"1","volume-title":"Proc. of IEEE HCS 32","author":"Arora Sonu","year":"2020","unstructured":"Sonu Arora, Dan Bouvier, and Chris Weaver. 2020. AMD next generation 7NM Ryzen\u2122 4000 APU \u201cRenoir\u201d. In Proc. of IEEE HCS 32. 1\u201330. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HCS49909.2020.9220414"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/320455.320457"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.5555\/1316689.1316777"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/2236584.2236593"},{"key":"e_1_3_2_13_2","first-page":"1","volume-title":"Proc. of IEEE HCS 32","author":"Blythe David","year":"2020","unstructured":"David Blythe. 2020. The Xe GPU architecture. In Proc. of IEEE HCS 32. IEEE Computer Society, 1\u201327. https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HCS49909.2020.9220591"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/2485278.2485283"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3035962"},{"key":"e_1_3_2_16_2","doi-asserted-by":"crossref","unstructured":"M. Bohr. 2007. A 30 year retrospective on Dennard\u2019s MOSFET scaling paper. 12 1 (2007) 11\u201313. https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/N-SSC.2007.4785534","DOI":"10.1109\/N-SSC.2007.4785534"},{"key":"e_1_3_2_17_2","volume-title":"Proc. of CIDR\u201905","author":"Boncz Peter A.","year":"2005","unstructured":"Peter A. Boncz, Marcin Zukowski, and Niels Nes. 2005. MonetDB\/X100: Hyper-pipelining query execution. In Proc. of CIDR\u201905."},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_3_2_19_2","first-page":"1","volume-title":"Proc. of IEEE HCS 26","author":"Bouvier Dan","year":"2014","unstructured":"Dan Bouvier and Ben Sander. 2014. Applying AMD\u2019s Kaveri APU for heterogeneous computing. In Proc. of IEEE HCS 26. 1\u201342. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2014.7478810"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.2"},{"key":"e_1_3_2_21_2","doi-asserted-by":"crossref","unstructured":"Sebastian Bre\u00df. 2014. The design and implementation of CoGaDB: A column-oriented GPU-accelerated DBMS. 14 3 (2014) 199\u2013209. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/s13222-014-0164-z","DOI":"10.1007\/s13222-014-0164-z"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.is.2013.05.004"},{"key":"e_1_3_2_23_2","first-page":"1891","volume-title":"Proc. of ACM SIGMOD\u201916","author":"Bre\u00df Sebastian","year":"2016","unstructured":"Sebastian Bre\u00df, Henning Funke, and Jens Teubner. 2016. Robust query processing in co-processor-accelerated databases. In Proc. of ACM SIGMOD\u201916. Association for Computing Machinery, 1891\u20131906. https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/2882903.2882936"},{"key":"e_1_3_2_24_2","doi-asserted-by":"crossref","unstructured":"Sebastian Bre\u00df Max Heimel Norbert Siegmund Ladjel Bellatreche and Gunter Saake. 2014. GPU-accelerated database systems: Survey and open challenges. Trans. Large Scale Data Knowl. Centered Syst. 15 (2014) 1\u201335. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/978-3-662-45761-0_1","DOI":"10.1007\/978-3-662-45761-0_1"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-018-0512-y"},{"key":"e_1_3_2_26_2","unstructured":"Paris Carbone Asterios Katsifodimos Stephan Ewen Volker Markl Seif Haridi and Kostas Tzoumas. 2015. Apache flink: Stream and batch processing in a single engine. IEEE Data Engineering Bulletin 36 4 (2015)."},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.5555\/3291168.3291211"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.14778\/3303753.3303760"},{"key":"e_1_3_2_29_2","first-page":"9","volume-title":"Proc. of CIDR\u201919","author":"Chrysogelos Periklis","year":"2019","unstructured":"Periklis Chrysogelos, Panagiotis Sioulas, and Anastasia Ailamaki. 2019. Hardware-conscious query processing in GPU-accelerated analytical engines. In Proc. of CIDR\u201919. 9. https:\/\/2.zoppoz.workers.dev:443\/http\/infoscience.epfl.ch\/record\/262529."},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/2187671.2187677"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"e_1_3_2_32_2","doi-asserted-by":"crossref","unstructured":"R. H. Dennard F. H. Gaensslen V. L. Rideout E. Bassous and A. R. LeBlanc. 1974. Design of ion-implanted MOSFET\u2019s with very small physical dimensions. IEEE Journal of Solid-State Circuits 9 5 (1974) 256\u2013268. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/JSSC.1974.1050511","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_33_2","first-page":"1086","volume-title":"Proc. of IEEE ICDE\u201916","author":"Doraiswamy Harish","year":"2016","unstructured":"Harish Doraiswamy, Huy T. Vo, Cl\u00e1udio T. Siva, and Juliana Freire. 2016. A GPU-based index to support interactive spatio-temporal queries over historical data. In Proc. of IEEE ICDE\u201916. 1086\u20131097. https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2016.7498315"},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1561\/1900000054"},{"key":"e_1_3_2_35_2","volume-title":"Proc. of ACM SIGGRAPH\/Eurographics\u201902 Tutorials","author":"Elder Gordon","year":"2002","unstructured":"Gordon Elder. 2002. Radeon 9700. In Proc. of ACM SIGGRAPH\/Eurographics\u201902 Tutorials. https:\/\/2.zoppoz.workers.dev:443\/https\/www.graphicshardware.org\/previous\/www_2002\/presentations\/Hot3D-RADEON9700.ppt."},{"key":"e_1_3_2_36_2","doi-asserted-by":"crossref","unstructured":"Jian Fang Yvo T. B. Mulder Jan Hidders Jinho Lee and H. Peter Hofstee. 2020. In-memory database acceleration on FPGAs: A survey. 29 1 (2020) 33\u201359. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/s00778-019-00581-w","DOI":"10.1007\/s00778-019-00581-w"},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.14778\/1920841.1920927"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3183734"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.14778\/3380750.3380758"},{"key":"e_1_3_2_40_2","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142511"},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1145\/1007568.1007594"},{"key":"e_1_3_2_42_2","first-page":"22","volume-title":"Proc. of IEEE SAC\u201991","author":"Graefe Goetz","year":"1991","unstructured":"Goetz Graefe and Leonard D. Shapiro. 1991. Data compression and database performance. In Proc. of IEEE SAC\u201991. IEEE Computer Society, 22\u201327. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/SOAC.1991.143840"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.5555\/2015039.2015535"},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.5555\/1032648.1033367"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1145\/1066157.1066201"},{"key":"e_1_3_2_46_2","volume-title":"Eurographics\u201904 Tutorials","author":"Harris Mark","year":"2004","unstructured":"Mark Harris. 2004. General-purpose computation using graphics hardware. In Eurographics\u201904 Tutorials. Eurographics Association. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.2312\/egt.20041034"},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362684"},{"key":"e_1_3_2_48_2","doi-asserted-by":"publisher","DOI":"10.1145\/1620585.1620588"},{"key":"e_1_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.1145\/1376616.1376670"},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.14778\/1952376.1952381"},{"key":"e_1_3_2_51_2","doi-asserted-by":"publisher","DOI":"10.14778\/2536206.2536216"},{"key":"e_1_3_2_52_2","doi-asserted-by":"publisher","DOI":"10.14778\/2735496.2735497"},{"key":"e_1_3_2_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2749438"},{"key":"e_1_3_2_54_2","doi-asserted-by":"publisher","DOI":"10.14778\/2536360.2536370"},{"key":"e_1_3_2_55_2","doi-asserted-by":"publisher","DOI":"10.5555\/3207796"},{"key":"e_1_3_2_56_2","doi-asserted-by":"publisher","DOI":"10.5555\/1941125"},{"key":"e_1_3_2_57_2","unstructured":"Zhe Jia Marco Maggioni Jeffrey Smith and Daniele Paolo Scarpazza. 2019. Dissecting the NVIDIA turing T4 GPU via microbenchmarking. abs\/1903.07486 (2019). https:\/\/2.zoppoz.workers.dev:443\/http\/arxiv.org\/abs\/1903.07486"},{"key":"e_1_3_2_58_2","unstructured":"Zhe Jia Marco Maggioni Benjamin Staiger and Daniele P. Scarpazza. 2018. Dissecting the NVIDIA Volta GPU architecture via microbenchmarking. abs\/1804.06826 (2018). https:\/\/2.zoppoz.workers.dev:443\/https\/arxiv.org\/abs\/1804.06826"},{"key":"e_1_3_2_59_2","doi-asserted-by":"publisher","DOI":"10.1145\/3154484"},{"key":"e_1_3_2_60_2","doi-asserted-by":"publisher","DOI":"10.1145\/2236584.2236592"},{"key":"e_1_3_2_61_2","doi-asserted-by":"publisher","DOI":"10.1145\/3076113.3076115"},{"key":"e_1_3_2_62_2","doi-asserted-by":"publisher","DOI":"10.14778\/3067421.3067423"},{"key":"e_1_3_2_63_2","first-page":"48","volume-title":"Proc. of EDBT\u201915 Workshops","author":"Karnagel Tomas","year":"2015","unstructured":"Tomas Karnagel, Dirk Habich, and Wolfgang Lehner. 2015. Local vs. global optimization: Operator placement strategies in heterogeneous environments. In Proc. of EDBT\u201915 Workshops. CEUR-WS.org, 48\u201355. https:\/\/2.zoppoz.workers.dev:443\/http\/ceur-ws.org\/Vol-1330\/paper-10.pdf."},{"key":"e_1_3_2_64_2","doi-asserted-by":"crossref","unstructured":"Tomas Karnagel Dirk Habich Benjamin Schlegel and Wolfgang Lehner. 2014. Heterogeneity-aware operator placement in column-store DBMS. Datenbank-Spektrum 14 3 (2014) 211\u2013221. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/s13222-014-0167-9","DOI":"10.1007\/s13222-014-0167-9"},{"key":"e_1_3_2_65_2","doi-asserted-by":"publisher","DOI":"10.1145\/2485278.2485280"},{"key":"e_1_3_2_66_2","first-page":"13","volume-title":"Proc. of ADMS@VLDB\u201915","author":"Karnagel Tomas","year":"2015","unstructured":"Tomas Karnagel, Ren\u00e9 M\u00fcller, and Guy M. Lohman. 2015. Optimizing GPU-accelerated group-by and aggregation. In Proc. of ADMS@VLDB\u201915. 13\u201324. https:\/\/2.zoppoz.workers.dev:443\/http\/www.adms-conf.org\/2015\/gpu-optimizer-camera-ready.pdf."},{"key":"e_1_3_2_67_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.62"},{"key":"e_1_3_2_68_2","doi-asserted-by":"publisher","DOI":"10.5555\/3275366.3284966"},{"key":"e_1_3_2_69_2","doi-asserted-by":"publisher","DOI":"10.5555\/3013620"},{"key":"e_1_3_2_70_2","unstructured":"Khronos OpenCL Working Group. 2013. The OpenCL Specification Version 2.0. https:\/\/2.zoppoz.workers.dev:443\/https\/www.khronos.org\/registry\/OpenCL\/specs\/opencl-2.0.pdf."},{"key":"e_1_3_2_71_2","volume-title":"Intel HPC Developer Conference\u201919","author":"Koduri Raja","year":"2019","unstructured":"Raja Koduri. 2019. Exascale for everyone. In Intel HPC Developer Conference\u201919. https:\/\/2.zoppoz.workers.dev:443\/https\/software.intel.com\/content\/www\/us\/en\/develop\/events\/hpc-devcon.html."},{"key":"e_1_3_2_72_2","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882906"},{"key":"e_1_3_2_73_2","doi-asserted-by":"publisher","DOI":"10.1145\/3329785.3329933"},{"key":"e_1_3_2_74_2","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882925"},{"key":"e_1_3_2_75_2","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_76_2","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2610507"},{"key":"e_1_3_2_77_2","first-page":"1","volume-title":"Proc. of IEEE HCS 23","author":"Lempel Oded","year":"2011","unstructured":"Oded Lempel. 2011. 2nd generation Intel\u00ae core processor family: Intel\u00ae core i7, i5 and i3. In Proc. of IEEE HCS 23. 1\u201348. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2011.7477509"},{"key":"e_1_3_2_78_2","first-page":"881","volume-title":"Proc. of IEEE ICDE\u201918","author":"Li Chuanwen","year":"2018","unstructured":"Chuanwen Li, Yu Gu, Jianzhong Qi, Jiayuan He, Qingxu Deng, and Ge Yu. 2018. A GPU accelerated update efficient index for kNN queries in road networks. In Proc. of IEEE ICDE\u201918. 881\u2013892. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2018.00084"},{"key":"e_1_3_2_79_2","unstructured":"Yuan Lin and Vinod Grover. 2018. Using CUDA Warp-Level Primitives. https:\/\/2.zoppoz.workers.dev:443\/https\/developer.nvidia.com\/blog\/using-cuda-warp-level-primitives\/."},{"key":"e_1_3_2_80_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_81_2","doi-asserted-by":"publisher","DOI":"10.1145\/383259.383274"},{"key":"e_1_3_2_82_2","unstructured":"LLVM Developer Group. [n.d.]. The LLVM Target-Independent Code Generator. https:\/\/2.zoppoz.workers.dev:443\/https\/www.llvm.org\/docs\/CodeGenerator.html."},{"key":"e_1_3_2_83_2","unstructured":"Justin Luitjens. 2014. Faster Parallel Reductions on Kepler. https:\/\/2.zoppoz.workers.dev:443\/https\/developer.nvidia.com\/blog\/faster-parallel-reductions-kepler\/."},{"key":"e_1_3_2_84_2","doi-asserted-by":"publisher","DOI":"10.1145\/3211922.3211925"},{"key":"e_1_3_2_85_2","doi-asserted-by":"publisher","DOI":"10.1145\/3318464.3389705"},{"key":"e_1_3_2_86_2","doi-asserted-by":"publisher","DOI":"10.5555\/1287369.1287387"},{"key":"e_1_3_2_87_2","first-page":"1","volume-title":"Proc. of IEEE HCS 31","author":"Mantor Mike","year":"2019","unstructured":"Mike Mantor. 2019. 7nm \u201cNavi\u201d GPU - A GPU built for performance and efficiency. In Proc. of IEEE HCS 31. IEEE Computer Society, 1\u201328. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2019.8875649"},{"key":"e_1_3_2_88_2","doi-asserted-by":"publisher","DOI":"10.1145\/882262.882362"},{"key":"e_1_3_2_89_2","doi-asserted-by":"publisher","DOI":"10.14778\/3151113.3151114"},{"key":"e_1_3_2_90_2","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2903735"},{"key":"e_1_3_2_91_2","doi-asserted-by":"publisher","DOI":"10.1145\/2788396"},{"key":"e_1_3_2_92_2","doi-asserted-by":"publisher","DOI":"10.1145\/2619228.2619230"},{"key":"e_1_3_2_93_2","first-page":"183","volume-title":"Proc. of IEEE ISPASS\u201916","author":"Mukherjee Saoni","year":"2016","unstructured":"Saoni Mukherjee, Yifan Sun, Paul Blinzer, Amir Kavyan Ziabari, and David Kaeli. 2016. A comprehensive performance analysis of HSA and OpenCL 2.0. In Proc. of IEEE ISPASS\u201916. 183\u2013193. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ISPASS.2016.7482093"},{"key":"e_1_3_2_94_2","doi-asserted-by":"publisher","DOI":"10.1145\/3230543.3230560"},{"key":"e_1_3_2_95_2","doi-asserted-by":"publisher","DOI":"10.14778\/2002938.2002940"},{"key":"e_1_3_2_96_2","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"e_1_3_2_97_2","volume-title":"CUDA C Best Practices Guide (v11.1 ed.)","author":"Corporation NVIDIA","year":"2020","unstructured":"NVIDIA Corporation. 2020. CUDA C Best Practices Guide (v11.1 ed.). https:\/\/2.zoppoz.workers.dev:443\/https\/docs.nvidia.com\/cuda\/pdf\/CUDA_C_Best_Practices_Guide.pdf."},{"key":"e_1_3_2_98_2","volume-title":"CUDA Toolkit Documentation","author":"Corporation NVIDIA","unstructured":"NVIDIA Corporation. [n.d.]. CUDA Toolkit Documentation. https:\/\/2.zoppoz.workers.dev:443\/https\/docs.nvidia.com\/cuda\/index.html."},{"key":"e_1_3_2_99_2","unstructured":"NVIDIA Corporation. 2020. NVIDIA A100 Tensor Core GPU Architecture."},{"key":"e_1_3_2_100_2","volume-title":"NVIDIA CUDA Programming Guide (version 1.0 ed.)","author":"Corporation NVIDIA","year":"2007","unstructured":"NVIDIA Corporation. 2007. NVIDIA CUDA Programming Guide (version 1.0 ed.)."},{"key":"e_1_3_2_101_2","unstructured":"NVIDIA Corporation. [n.d.]. NVIDIA GPUDirect. https:\/\/2.zoppoz.workers.dev:443\/https\/developer.nvidia.com\/gpudirect."},{"key":"e_1_3_2_102_2","unstructured":"NVIDIA Corporation. 2016. NVIDIA Tesla P100."},{"key":"e_1_3_2_103_2","unstructured":"NVIDIA Corporation. 2017. NVIDIA Tesla V100 GPU Architecture."},{"key":"e_1_3_2_104_2","unstructured":"NVIDIA Corporation. 2018. NVIDIA Turing GPU Architecture."},{"key":"e_1_3_2_105_2","unstructured":"NVIDIA Corporation. 2009. NVIDIA\u2019s Next Generation CUDA Compute Architecture: Fermi."},{"key":"e_1_3_2_106_2","unstructured":"Patrick O\u2019Neil Eizabeth O\u2019Neil and Xuedong Chen. 2009. Star Schema Benchmark-Revision 3. https:\/\/2.zoppoz.workers.dev:443\/http\/www.cs.umbo.edu\/poneil\/StarSchemaB.PDF."},{"key":"e_1_3_2_107_2","unstructured":"Oak Ridge National Laboratory. 2019. Frontier Spec Sheet. https:\/\/2.zoppoz.workers.dev:443\/https\/www.olcf.ornl.gov\/wp-content\/uploads\/2019\/05\/frontier_specsheet.pdf."},{"key":"e_1_3_2_108_2","first-page":"1","volume-title":"Proc. of IEEE HCS 32","author":"Papazian Irma Esmer","year":"2020","unstructured":"Irma Esmer Papazian. 2020. New 3rd gen Intel\u00ae Xeon\u00ae scalable processor (codename: Ice Lake-SP). In Proc. of IEEE HCS 32. IEEE Computer Society, 1\u201322. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HCS49909.2020.9220434"},{"key":"e_1_3_2_109_2","unstructured":"Mark Papermaster. 2020. Future of High Performance. https:\/\/2.zoppoz.workers.dev:443\/https\/ir.amd.com\/news-events\/analyst-day."},{"key":"e_1_3_2_110_2","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2915224"},{"key":"e_1_3_2_111_2","first-page":"508","volume-title":"Proc. of IEEE ICDE\u201914","author":"Pirk Holger","year":"2014","unstructured":"Holger Pirk, Stefan Manegold, and Martin Kersten. 2014. Waste not... efficient co-processing of relational data. In Proc. of IEEE ICDE\u201914. 508\u2013519. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2014.6816677"},{"key":"e_1_3_2_112_2","doi-asserted-by":"publisher","DOI":"10.14778\/3007328.3007336"},{"key":"e_1_3_2_113_2","doi-asserted-by":"publisher","DOI":"10.1145\/2236584.2236591"},{"key":"e_1_3_2_114_2","first-page":"97","volume-title":"Proc. of TPCTC\u201914","author":"Psaroudakis Iraklis","year":"2015","unstructured":"Iraklis Psaroudakis, Florian Wolf, Norman May, Thomas Neumann, Alexander B\u00f6hm, Anastasia Ailamaki, and Kai-Uwe Sattler. 2015. Scaling up mixed workloads: A battle of data freshness, flexibility, and scheduling. In Proc. of TPCTC\u201914. Springer International Publishing, 97\u2013112. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1007\/978-3-319-15350-6_7"},{"key":"e_1_3_2_115_2","volume-title":"Proc. of CIDR\u201920","author":"Raza Syed Mohammad Aunn","year":"2020","unstructured":"Syed Mohammad Aunn Raza, Periklis Chrysogelos, Panagiotis Sioulas, Vladimir Indjic, Angelos Christos Anadiotis, and Anastasia Ailamaki. 2020. GPU-accelerated data management under the test of time. In Proc. of CIDR\u201920."},{"key":"e_1_3_2_116_2","first-page":"1","volume-title":"Proc. of IEEE HCS 25","author":"Rogers Phil","year":"2013","unstructured":"Phil Rogers. 2013. Heterogeneous system architecture overview. In Proc. of IEEE HCS 25. 1\u201341. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2013.7478286"},{"key":"e_1_3_2_117_2","first-page":"1","volume-title":"Proc. of IEEE HCS 25","author":"Rogers Phil","year":"2013","unstructured":"Phil Rogers, Ben Ander, Benedict Gaster, and Ian Bratt. 2013. Heterogeneous system architecture (HSA): Overview and implementation. In Proc. of IEEE HCS 25. 1\u201341. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HOTCHIPS.2013.7478286"},{"key":"e_1_3_2_118_2","doi-asserted-by":"publisher","DOI":"10.1145\/3329785.3329922"},{"key":"e_1_3_2_119_2","first-page":"1","volume-title":"Proc. of ADMS@VLDB\u201915","author":"Rosenfeld Viktor","year":"2015","unstructured":"Viktor Rosenfeld, Max Heimel, Christoph Viebig, and Volker Markl. 2015. The operator variant selection problem on heterogeneous hardware. In Proc. of ADMS@VLDB\u201915. 1\u201312. https:\/\/2.zoppoz.workers.dev:443\/http\/www.adms-conf.org\/2015\/ADMS_Viktor_Rosenfeld_CR.pdf."},{"key":"e_1_3_2_120_2","doi-asserted-by":"publisher","DOI":"10.1145\/3076113.3076122"},{"key":"e_1_3_2_121_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.40"},{"key":"e_1_3_2_122_2","volume-title":"GPU Tech Conference 2018","author":"Sakharnykh Nikolay","year":"2018","unstructured":"Nikolay Sakharnykh. 2018. Everything you need to know about unified memory. In GPU Tech Conference 2018. https:\/\/2.zoppoz.workers.dev:443\/https\/on-demand.gputechconf.com\/gtc\/2018\/presentation\/s8430-everything-you-need-to-know-about-unified-memory.pdf."},{"key":"e_1_3_2_123_2","doi-asserted-by":"crossref","unstructured":"Science Staff. 2011. Special online collection: Dealing with data. challenges and opportunities. Science 331 6018 (2011) 692\u2013693. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1126\/science.331.6018.692","DOI":"10.1126\/science.331.6018.692"},{"key":"e_1_3_2_124_2","doi-asserted-by":"publisher","DOI":"10.5555\/1280094.1280110"},{"key":"e_1_3_2_125_2","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882918"},{"key":"e_1_3_2_126_2","unstructured":"Debendra Das Sharma and Siamak Tavallaei. 2020. Compute Express Link\u2122 2.0 White Paper."},{"key":"e_1_3_2_127_2","first-page":"698","volume-title":"Proc. of IEEE ICDE\u201919","author":"Sioulas Panagiotis","year":"2019","unstructured":"Panagiotis Sioulas, Periklis Chrysogelos, Manos Karpathiotakis, Raja Appuswamy, and Anastasia Ailamaki. 2019. Hardware-conscious hash-joins on GPUs. In Proc. of IEEE ICDE\u201919. 698\u2013709. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2019.00068"},{"key":"e_1_3_2_128_2","doi-asserted-by":"publisher","DOI":"10.1145\/2212908.2212924"},{"key":"e_1_3_2_129_2","first-page":"1","volume-title":"Proc. of IEEE HCS 32","author":"Starke William","year":"2020","unstructured":"William Starke and Brian Thompto. 2020. IBM\u2019s POWER10 processor. In Proc. of IEEE HCS 32. IEEE Computer Society, 1\u201343. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HCS49909.2020.9220618"},{"key":"e_1_3_2_130_2","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3064043"},{"key":"e_1_3_2_131_2","doi-asserted-by":"publisher","DOI":"10.5555\/2220077.2220227"},{"key":"e_1_3_2_132_2","doi-asserted-by":"crossref","unstructured":"David Suggs Mahesh Subramony and Dan Bouvier. 2020. The AMD \u201cZen 2\u201d processor. IEEE Micro 40 2 (2020) 45\u201352. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/MM.2020.2974217","DOI":"10.1109\/MM.2020.2974217"},{"key":"e_1_3_2_133_2","doi-asserted-by":"publisher","DOI":"10.1145\/872757.872813"},{"key":"e_1_3_2_134_2","volume-title":"Data, Data Everywhere. A Special Report on Managing Information.","author":"Economist The","year":"2010","unstructured":"The Economist. 2010. Data, Data Everywhere. A Special Report on Managing Information.https:\/\/2.zoppoz.workers.dev:443\/https\/www.economist.com\/special-report\/2010\/02\/27\/data-data-everywhere."},{"key":"e_1_3_2_135_2","unstructured":"The Khronos Group. [n.d.]. The Open Standard for Parallel Programming of Heterogeneous Systems. https:\/\/2.zoppoz.workers.dev:443\/https\/www.khronos.org\/opencl\/."},{"key":"e_1_3_2_136_2","volume-title":"TPC-H Version 2 and Version 3","year":"2021","unstructured":"TPC. 2021. TPC-H Version 2 and Version 3. https:\/\/2.zoppoz.workers.dev:443\/http\/www.tpc.org\/tpch\/."},{"key":"e_1_3_2_137_2","first-page":"1","volume-title":"Proc. of IEEE HCS 32","author":"Vera Xavier","year":"2020","unstructured":"Xavier Vera. 2020. Inside Tiger Lake: Intel\u2019s next generation mobile client CPU. In Proc. of IEEE HCS 32. 1\u201326. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/HCS49909.2020.9220443"},{"key":"e_1_3_2_138_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00075"},{"key":"e_1_3_2_139_2","unstructured":"David W. Wall. 1993. Limits of Instruction-Level Parallelism."},{"key":"e_1_3_2_140_2","doi-asserted-by":"publisher","DOI":"10.14778\/2350229.2350268"},{"key":"e_1_3_2_141_2","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_142_2","doi-asserted-by":"publisher","DOI":"10.14778\/2536206.2536210"},{"key":"e_1_3_2_143_2","doi-asserted-by":"publisher","DOI":"10.14778\/3157794.3157803"},{"key":"e_1_3_2_144_2","volume-title":"Proc. of Eurographics\u201904 Tutorials","author":"Zeller Cyril","year":"2004","unstructured":"Cyril Zeller, Randy Fernando, Matthias Wloka, and Mark Harris. 2004. Programming graphics hardware. In Proc. of Eurographics\u201904 Tutorials. Eurographics Association. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.2312\/egt.20041034"},{"key":"e_1_3_2_145_2","first-page":"1037","volume-title":"Proc. of IEEE ICDE\u201918","author":"Zhang Bowen","year":"2018","unstructured":"Bowen Zhang, Yanyan Shen, Yanmin Zhu, and Jiadi Yu. 2018. A GPU-accelerated framework for processing trajectory queries. In Proc. of IEEE ICDE\u201918. 1037\u20131048. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2018.00097"},{"key":"e_1_3_2_146_2","doi-asserted-by":"publisher","DOI":"10.5555\/3489146.3489189"},{"key":"e_1_3_2_147_2","first-page":"671","volume-title":"Proc. of IEEE ICDE\u201917","author":"Zhang Kai","year":"2017","unstructured":"Kai Zhang, Jiayu Hu, Bingsheng He, and Bei Hua. 2017. DIDO: Dynamic pipelines for in-memory key-value stores on coupled CPU-GPU architectures. In Proc. of IEEE ICDE\u201917. 671\u2013682. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2017.120"},{"key":"e_1_3_2_148_2","doi-asserted-by":"publisher","DOI":"10.14778\/2809974.2809984"},{"key":"e_1_3_2_149_2","first-page":"59","volume-title":"Proc. of IEEE ICDE\u201906","author":"Zukowski Marcin","year":"2006","unstructured":"Marcin Zukowski, S\u00e1ndor H\u00e9man, Niels Nes, and Peter Boncz. 2006. Super-scalar RAM-CPU cache compression. In Proc. of IEEE ICDE\u201906. 59\u201359. DOI:https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1109\/ICDE.2006.150"}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3485126","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/3485126","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:18:35Z","timestamp":1750191515000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3485126"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":148,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2023,1,31]]}},"alternative-id":["10.1145\/3485126"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/3485126","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"value":"0360-0300","type":"print"},{"value":"1557-7341","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1,17]]},"assertion":[{"value":"2020-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-01-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}