{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,13]],"date-time":"2026-04-13T23:16:22Z","timestamp":1776122182065,"version":"3.50.1"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T00:00:00Z","timestamp":1740355200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,5,31]]},"abstract":"<jats:p>FPGAs are being challenged by various security threats, including reverse engineering attacks, hardware tampering, and side-channel analysis attacks. Although the existing static obfuscation methods can protect FPGA systems from IP piracy and hardware tampering, limited work is available to improve the attack resilience of obfuscation modules. As hardware Trojans are one of the most significant hardware tampering attacks on FPGAs, this work aims for the specific hardware Trojan that attempts to nullify design obfuscation. To address this need, we leverage the advanced function of FPGA CAD tools to propose a Dynamic Partial Reconfiguration enabled Design Obfuscation (DPReDO) method. Our method partially modifies the FPGA bitstream at runtime to remove the sabotaged obfuscation variant, thus offering enhanced attack resilience against hardware Trojans. Experimental results based on ISCAS and ITC-99 benchmark circuits show that the DPReDO method reduces the Trojan hit rate by up to 80% over existing static obfuscation with less than 3% hardware overhead. To test the practical feasibility of the proposed countermeasure, we further apply DPReDO to an FPGA-accelerated computation engine for a financial application. Compared to static obfuscation, the proposed DPReDO only incurs 2.6% and 1.2% more FPGA LUTs and slices, respectively.<\/jats:p>","DOI":"10.1145\/3716502","type":"journal-article","created":{"date-parts":[[2025,2,6]],"date-time":"2025-02-06T07:11:26Z","timestamp":1738825886000},"page":"1-25","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A New Dynamic Countermeasure to Strengthen Design Obfuscation in FPGAs"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0009-0009-0644-3033","authenticated-orcid":false,"given":"Sandeep","family":"Sunkavilli","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of New Hampshire, Durham, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0009-0007-3045-3923","authenticated-orcid":false,"given":"Nishanth","family":"Chennagouni","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, University of New Hampshire, Durham, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-7232-8529","authenticated-orcid":false,"given":"Qiaoyan","family":"Yu","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, University of New Hampshire, Durham, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,2,24]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"2022. Field Programmable Gate Array (FPGA) Market Size \u2014 mordorintelligence.com. Retrieved May 16 2023 from https:\/\/2.zoppoz.workers.dev:443\/https\/www.mordorintelligence.com\/industry-reports\/field-programmable-gate-array-fpga-market\/market-size. (2022)."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2013.2247460"},{"key":"e_1_3_1_4_2","doi-asserted-by":"crossref","first-page":"287","DOI":"10.1145\/2591513.2591520","volume-title":"Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI.","author":"Mal-Sarkar Sanchita","year":"2014","unstructured":"Sanchita Mal-Sarkar, Aswin Krishna, Anandaroop Ghosh, and Swarup Bhunia. 2014. Hardware trojan attacks in FPGA devices: Threat analysis and effective counter measures. In Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI.Association for Computing Machinery, New York, NY, USA, 287\u2013292. DOI:10.1145\/2591513.2591520"},{"key":"e_1_3_1_5_2","first-page":"202","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications","author":"Mirzargar Seyedeh Sharareh","year":"2019","unstructured":"Seyedeh Sharareh Mirzargar and Mirjana Stojilovi\u0107. 2019. Physical side-channel attacks and covert communication on FPGAs: A survey. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications. 202\u2013210. DOI:10.1109\/FPL.2019.00039"},{"key":"e_1_3_1_6_2","first-page":"45","volume-title":"Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines","author":"Ramesh Chethan","year":"2018","unstructured":"Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sebastien Pillement, Daniel Holcomb, and Russell Tessier. 2018. FPGA side channel attacks without physical access. In Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines. 45\u201352. DOI:10.1109\/FCCM.2018.00016"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2646367"},{"key":"e_1_3_1_8_2","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/FDTC.2019.00015","volume-title":"Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography","author":"Alam Md Mahbub","year":"2019","unstructured":"Md Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark Tehranipoor, and Domenic Forte. 2019. RAM-Jam: Remote temperature and voltage fault attack on FPGAs using memory collisions. In Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography. 48\u201355. DOI:10.1109\/FDTC.2019.00015"},{"key":"e_1_3_1_9_2","doi-asserted-by":"crossref","first-page":"293","DOI":"10.1145\/2902961.2903033","volume-title":"Proceedings of the 26th Edition on Great Lakes Symposium on VLSI.","author":"Mirian Vincent","year":"2016","unstructured":"Vincent Mirian and Paul Chow. 2016. Extracting designs of secure IPs using FPGA CAD tools. In Proceedings of the 26th Edition on Great Lakes Symposium on VLSI.Association for Computing Machinery, New York, NY, USA, 293\u2013298. DOI:10.1145\/2902961.2903033"},{"key":"e_1_3_1_10_2","first-page":"328","volume-title":"Proceedings of the 2022 19th International SoC Design Conference","author":"Cho Mannhee","year":"2022","unstructured":"Mannhee Cho, Dongchan Lee, Sanghyun Lee, Youngmin Kim, and Hyung-Min Lee. 2022. Automated reverse engineering tools for FPGA bitstream extraction and logic estimation. In Proceedings of the 2022 19th International SoC Design Conference. 328\u2013329. DOI:10.1109\/ISOCC56007.2022.10031326"},{"key":"e_1_3_1_11_2","first-page":"382","volume-title":"Proceedings of the Cryptographic Hardware and Embedded Systems","author":"Lin Lang","year":"2009","unstructured":"Lang Lin, Markus Kasper, Tim G\u00fcneysu, Christof Paar, and Wayne Burleson. 2009. Trojan side-channels: Lightweight hardware trojans through side-channel engineering. In Proceedings of the Cryptographic Hardware and Embedded Systems. Christophe Clavier and Kris Gaj (Eds.). Springer, Berlin, 382\u2013395."},{"key":"e_1_3_1_12_2","first-page":"396","volume-title":"Proceedings of the Cryptographic Hardware and Embedded Systems.","author":"Chakraborty Rajat Subhra","year":"2009","unstructured":"Rajat Subhra Chakraborty, Francis Wolff, Somnath Paul, Christos Papachristou, and Swarup Bhunia. 2009. MERO: A statistical approach for hardware trojan detection. In Proceedings of the Cryptographic Hardware and Embedded Systems.Christophe Clavier and Kris Gaj (Eds.). Springer, Berlin, 396\u2013410."},{"key":"e_1_3_1_13_2","first-page":"69","volume-title":"Proceedings of the 2015 IEEE 26th International Symposium on Software Reliability Engineering.","author":"Kitsos Paris","year":"2015","unstructured":"Paris Kitsos, Dimitris E. Simos, Jose Torres-Jimenez, and Artemios G. Voyiatzis. 2015. Exciting FPGA cryptographic trojans using combinatorial testing. In Proceedings of the 2015 IEEE 26th International Symposium on Software Reliability Engineering.69\u201376. DOI:10.1109\/ISSRE.2015.7381800"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2727985"},{"key":"e_1_3_1_15_2","first-page":"13","volume-title":"Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust","author":"Narasimhan Seetharam","year":"2010","unstructured":"Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis Wolff1, Christos Papachristou, Kaushik Roy, and Swarup Bhunia. 2010. Multiple-parameter side-channel analysis: A non-invasive hardware trojan detection approach. In Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust. 13\u201318. DOI:10.1109\/HST.2010.5513122"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2584052"},{"key":"e_1_3_1_17_2","first-page":"190","volume-title":"Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.","author":"Salmani Hassan","year":"2013","unstructured":"Hassan Salmani and Mohammed Tehranipoor. 2013. Analyzing circuit vulnerability to hardware trojan insertion at the behavioral level. In Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.190\u2013195. DOI:10.1109\/DFT.2013.6653605"},{"key":"e_1_3_1_18_2","doi-asserted-by":"crossref","first-page":"114","DOI":"10.1109\/AHS.2008.67","volume-title":"Proceedings of the 2008 NASA\/ESA Conference on Adaptive Hardware and Systems","author":"Shinohara Kouji","year":"2008","unstructured":"Kouji Shinohara and Minoru Watanabe. 2008. A double or triple module redundancy model exploiting dynamic reconfigurations. In Proceedings of the 2008 NASA\/ESA Conference on Adaptive Hardware and Systems. 114\u2013121. DOI:10.1109\/AHS.2008.67"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2343259"},{"key":"e_1_3_1_20_2","first-page":"1","volume-title":"Proceedings of the Topics in Cryptology","author":"Moradi Amir","year":"2012","unstructured":"Amir Moradi, Markus Kasper, and Christof Paar. 2012. Black-box side-channel attacks highlight the importance of countermeasures. In Proceedings of the Topics in Cryptology. Orr Dunkelman (Ed.). Springer, Berlin, 1\u201318."},{"key":"e_1_3_1_21_2","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1145\/2435264.2435282","volume-title":"Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays.","author":"Moradi Amir","year":"2013","unstructured":"Amir Moradi, David Oswald, Christof Paar, and Pawel Swierczynski. 2013. Side-channel attacks on the bitstream encryption mechanism of altera stratix II: Facilitating black-box analysis using software reverse-engineering. In Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays.Association for Computing Machinery, New York, NY, USA, 91\u2013100. DOI:10.1145\/2435264.2435282"},{"key":"e_1_3_1_22_2","first-page":"1803","volume-title":"Proceedings of the 29th USENIX Conference on Security Symposium","author":"Ender Maik","year":"2020","unstructured":"Maik Ender, Amir Moradi, and Christof Paar. 2020. The unpatchable silicon: A full break of the bitstream encryption of xilinx 7-series fpgas. In Proceedings of the 29th USENIX Conference on Security Symposium. 1803\u20131819."},{"key":"e_1_3_1_23_2","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1109\/HST.2015.7140252","volume-title":"Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust","author":"Subramanyan Pramod","year":"2015","unstructured":"Pramod Subramanyan, Sayak Ray, and Sharad Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust. 137\u2013143. DOI:10.1109\/HST.2015.7140252"},{"key":"e_1_3_1_24_2","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/AsianHOST.2018.8607163","volume-title":"Proceedings of the 2018 Asian Hardware Oriented Security and Trust Symposium","author":"Chakraborty Prabuddha","year":"2018","unstructured":"Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia. 2018. SAIL: Machine learning guided structural analysis attack on hardware obfuscation. In Proceedings of the 2018 Asian Hardware Oriented Security and Trust Symposium. 56\u201361. DOI:10.1109\/AsianHOST.2018.8607163"},{"key":"e_1_3_1_25_2","first-page":"9","volume-title":"Proceedings of the 2020 Workshop on DYnamic and Novel Advances in Machine Learning and Intelligent Cyber Security.","author":"Yu Yang","year":"2022","unstructured":"Yang Yu, Michail Moraitis, and Elena Dubrova. 2022. Why deep learning makes it difficult to keep secrets in FPGAs. In Proceedings of the 2020 Workshop on DYnamic and Novel Advances in Machine Learning and Intelligent Cyber Security.Association for Computing Machinery, New York, NY, USA, 9 pages. DOI:10.1145\/3477997.3478001"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.945306"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2015.2400413"},{"key":"e_1_3_1_28_2","first-page":"611","volume-title":"Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference.","author":"Karam Robert","year":"2017","unstructured":"Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, and Swarup Bhunia. 2017. MUTARCH: Architectural diversity for FPGA device and IP security. In Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference.611\u2013616. DOI:10.1109\/ASPDAC.2017.7858391"},{"key":"e_1_3_1_29_2","first-page":"1","volume-title":"Proceedings of the 2014 International Test Conference","author":"Pino Youngok","year":"2014","unstructured":"Youngok Pino, Vinayaka Jyothi, and Matthew French. 2014. Intra-die process variation aware anomaly detection in FPGAs. In Proceedings of the 2014 International Test Conference. 1\u20136. DOI:10.1109\/TEST.2014.7035343"},{"key":"e_1_3_1_30_2","doi-asserted-by":"crossref","first-page":"260","DOI":"10.23919\/DATE.2019.8714801","volume-title":"Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition","author":"Hettwer Benjamin","year":"2019","unstructured":"Benjamin Hettwer, Johannes Petersen, Stefan Gehrer, Heike Neumann, and Tim G\u00fcneysu. 2019. Securing cryptographic circuits by exploiting implementation diversity and partial reconfiguration on FPGAs. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition. 260\u2013263. DOI:10.23919\/DATE.2019.8714801"},{"key":"e_1_3_1_31_2","first-page":"6","volume-title":"Proceedings of the 56th Annual Design Automation Conference 2019.","author":"Jayasinghe Darshana","year":"2019","unstructured":"Darshana Jayasinghe, Aleksandar Ignjatovic, and Sri Parameswaran. 2019. RFTC: Runtime frequency tuning countermeasure using FPGA dynamic reconfiguration to mitigate power analysis attacks. In Proceedings of the 56th Annual Design Automation Conference 2019.Association for Computing Machinery, New York, NY, USA, 6 pages. DOI:10.1145\/3316781.3317899"},{"key":"e_1_3_1_32_2","first-page":"200","volume-title":"Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications","author":"Hettwer Benjamin","year":"2020","unstructured":"Benjamin Hettwer, Kallyan Das, Sebastien Leger, Stefan Gehrer, and Tim G\u00fcneysu. 2020. Lightweight side-channel protection using dynamic clock randomization. In Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications. 200\u2013207. DOI:10.1109\/FPL50879.2020.00041"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2879878"},{"key":"e_1_3_1_34_2","first-page":"401","volume-title":"Proceedings of the 2018 19th International Symposium on Quality Electronic Design","author":"Zhang Zhiming","year":"2018","unstructured":"Zhiming Zhang, Laurent Njilla, Charles Kamhoua, Kevin Kwiat, and Qiaoyan Yu. 2018. Securing FPGA-based obsolete component replacement for legacy systems. In Proceedings of the 2018 19th International Symposium on Quality Electronic Design. 401\u2013406. DOI:10.1109\/ISQED.2018.8357320"},{"key":"e_1_3_1_35_2","first-page":"1","volume-title":"Proceedings of the 2022 IEEE 35th International System-on-Chip Conference","author":"Sunkavilli Sandeep","year":"2022","unstructured":"Sandeep Sunkavilli, Nishanth Goud Chennagouni, and Qiaoyan Yu. 2022. DPReDO: Dynamic partial reconfiguration enabled design obfuscation for FPGA security. In Proceedings of the 2022 IEEE 35th International System-on-Chip Conference. 1\u20136. DOI:10.1109\/SOCC56010.2022.9908070"},{"key":"e_1_3_1_36_2","first-page":"33","volume-title":"Proceedings of the 2022 IEEE International Symposium on Hardware Oriented Security and Trust","author":"Sunkavilli Sandeep","year":"2022","unstructured":"Sandeep Sunkavilli and Qiaoyan Yu. 2022. Security threats and countermeasure deployment using partial reconfiguration in FPGA CAD tools. In Proceedings of the 2022 IEEE International Symposium on Hardware Oriented Security and Trust. 33\u201336. DOI:10.1109\/HOST54066.2022.9839731"},{"key":"e_1_3_1_37_2","first-page":"504","volume-title":"Proceedings of the 2021 22nd International Symposium on Quality Electronic Design","author":"Sunkavilli Sandeep","year":"2021","unstructured":"Sandeep Sunkavilli, Zhiming Zhang, and Qiaoyan Yu. 2021. Analysis of attack surfaces and practical attack examples in open source FPGA CAD tools. In Proceedings of the 2021 22nd International Symposium on Quality Electronic Design. 504\u2013509. DOI:10.1109\/ISQED51717.2021.9424291"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/3315574"},{"key":"e_1_3_1_39_2","first-page":"231","volume-title":"Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications","author":"Provelengios George","year":"2020","unstructured":"George Provelengios, Daniel Holcomb, and Russell Tessier. 2020. Power wasting circuits for cloud FPGA attacks. In Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications. 231\u2013235. DOI:10.1109\/FPL50879.2020.00046"},{"key":"e_1_3_1_40_2","doi-asserted-by":"crossref","first-page":"1745","DOI":"10.23919\/DATE.2019.8715263","volume-title":"Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition","author":"Mahmoud Dina","year":"2019","unstructured":"Dina Mahmoud and Mirjana Stojilovi\u0107. 2019. Timing violation induced faults in multi-tenant FPGAs. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition. 1745\u20131750. DOI:10.23919\/DATE.2019.8715263"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-16344-9_14"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1145\/3451236"},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"e_1_3_1_44_2","article-title":"Partial reconfiguration of Xilinx FPGAs using ISE design suite","author":"Dye David","year":"2012","unstructured":"David Dye. 2012. Partial reconfiguration of Xilinx FPGAs using ISE design suite. White Paper (2012).","journal-title":"White Paper"},{"key":"e_1_3_1_45_2","first-page":"39","article-title":"The ISCAS\u201985 benchmark circuits and netlist format","volume":"25","author":"Bryan David","year":"1985","unstructured":"David Bryan. 1985. The ISCAS\u201985 benchmark circuits and netlist format. North Carolina State University 25 (1985), 39.","journal-title":"North Carolina State University"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3179304"},{"key":"e_1_3_1_48_2","first-page":"171","volume-title":"Proceedings of the 2019 Great Lakes Symposium on VLSI.","author":"Hu Bo","year":"2019","unstructured":"Bo Hu, Jingxiang Tian, Mustafa Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrion Schaefer, and Carl Sechen. 2019. Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded FPGA. In Proceedings of the 2019 Great Lakes Symposium on VLSI.Association for Computing Machinery, New York, NY, USA, 171\u2013176. DOI:10.1145\/3299874.3317992"},{"key":"e_1_3_1_49_2","doi-asserted-by":"crossref","first-page":"468","DOI":"10.1109\/ReConFig.2011.11","volume-title":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs","author":"Schryver Christian de","year":"2011","unstructured":"Christian de Schryver, Ivan Shcherbakov, Frank Kienle, Norbert Wehn, Henning Marxen, Anton Kostiuk, and Ralf Korn. 2011. An energy efficient FPGA accelerator for monte carlo option pricing with the heston model. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs. 468\u2013474. DOI:10.1109\/ReConFig.2011.11"},{"issue":"3","key":"e_1_3_1_50_2","article-title":"High performance monte-carlo based option pricing on FPGAs.","volume":"16","author":"Tian Xiang","year":"2008","unstructured":"Xiang Tian, Khaled Benkrid, and Xiaochen Gu. 2008. High performance monte-carlo based option pricing on FPGAs. Engineering Letters 16, 3 (2008).","journal-title":"Engineering Letters"},{"key":"e_1_3_1_51_2","first-page":"953","volume-title":"Proceedings of the 2012 Design, Automation and Test in Europe Conference and Exhibition","author":"Rajendran Jeyavijayan","year":"2012","unstructured":"Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2012. Logic encryption: A fault analysis perspective. In Proceedings of the 2012 Design, Automation and Test in Europe Conference and Exhibition. 953\u2013958. DOI:10.1109\/DATE.2012.6176634"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3716502","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/pdf\/10.1145\/3716502","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:19:10Z","timestamp":1750295950000},"score":1,"resource":{"primary":{"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/dl.acm.org\/doi\/10.1145\/3716502"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,24]]},"references-count":50,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025,5,31]]}},"alternative-id":["10.1145\/3716502"],"URL":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/3716502","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2,24]]},"assertion":[{"value":"2024-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-01-18","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-02-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}