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Improving the performance of sorting operations can have a significant impact on many application domains. Much attention has been paid to hardware-based solutions for high-performance sorting. These are often realized with application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Recently, in-memory sorting solutions have also been proposed to address the movement cost issue between memory and processing units, also known as the Von Neumann bottleneck. Due to the complexity of the sorting algorithms, achieving an efficient hardware implementation for sorting data is challenging. A large body of prior solutions is built on compare-and-swap (CAS) units. These are categorized as\n            <jats:italic>comparison-based<\/jats:italic>\n            sorting. Some recent solutions offer\n            <jats:italic>comparison-free<\/jats:italic>\n            sorting. In this survey, we review the latest works in the area of hardware-based sorting. We also discuss the recent hardware solutions for\n            <jats:italic>partial<\/jats:italic>\n            and\n            <jats:italic>stream<\/jats:italic>\n            sorting. Finally, we discuss some important concerns that need to be considered in the future designs of sorting systems.\n          <\/jats:p>","DOI":"10.1145\/3734797","type":"journal-article","created":{"date-parts":[[2025,5,5]],"date-time":"2025-05-05T11:29:02Z","timestamp":1746444542000},"page":"1-31","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Sorting it out in Hardware: A State-of-the-Art Survey"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-7641-6606","authenticated-orcid":false,"given":"Amir","family":"Jalilvand","sequence":"first","affiliation":[{"name":"School of Computing and Informatics, University of Louisiana at Lafayette, Lafayette, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0009-0004-8569-4423","authenticated-orcid":false,"given":"Faeze S.","family":"Banitaba","sequence":"additional","affiliation":[{"name":"School of Computing and Informatics, University of Louisiana at Lafayette, Lafayette United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0001-5811-3655","authenticated-orcid":false,"given":"S. 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