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This article investigates a representative dataflow toolchain, the StreamBlock compiler for the CAL actor language, along with its Actor Machine (AM) Intermediate Representation (IR), identifying limitations in handling parametric application specifications.<\/jats:p>\n                  <jats:p>To address these limitations, we extend CAL to support parametric actor and network specifications allowing a single description to capture multiple problem sizes. We demonstrate these extensions with a parametric QR Decomposition application and benchmarks from the Savina Actor Benchmark Suite.<\/jats:p>\n                  <jats:p>When compiling actor specifications to software or hardware, the AM IR is used for optimisation purposes. The AM defines a controller specifying how actors should behave at runtime. We show that as the complexity of the actor increases, the AM model scales poorly, leading to compilation failing. In this work, we improve the AM model enabling the compilation of actors up to six times larger than previously possible.<\/jats:p>\n                  <jats:p>For specifications targeting FPGAs, we offer an alternative to the AM designed to take better advantage of available hardware parallelism. Our results show that this controller scales better with the size of the actor compared to the AM controller, reducing latency significantly for a slight increase in resources used.<\/jats:p>\n                  <jats:p>These contributions extend CAL\u2019s applicability, making it easier to specify and scale a broader range of streaming applications.<\/jats:p>","DOI":"10.1145\/3774886","type":"journal-article","created":{"date-parts":[[2025,11,5]],"date-time":"2025-11-05T11:45:03Z","timestamp":1762343103000},"page":"1-26","update-policy":"https:\/\/2.zoppoz.workers.dev:443\/https\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Specifying and Compiling Scalable Networks of Actors for Software and Hardware Platforms"],"prefix":"10.1145","volume":"25","author":[{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0002-9835-4741","authenticated-orcid":false,"given":"Gareth","family":"Callanan","sequence":"first","affiliation":[{"name":"Computer Science, Lund University","place":["Lund, Sweden"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/2.zoppoz.workers.dev:443\/https\/orcid.org\/0000-0003-1739-3384","authenticated-orcid":false,"given":"Flavius","family":"Gruian","sequence":"additional","affiliation":[{"name":"Computer Science, Lund University","place":["Lund, Sweden"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,1,8]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.7551\/mitpress\/1086.001.0001"},{"key":"e_1_3_2_3_2","volume-title":"Vitis High-Level Synthesis (HLS) User Guide (UG1399)","author":"Xilinx AMD","year":"2023","unstructured":"AMD Xilinx. 2023. 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