{"id":"https://openalex.org/W2154185188","doi":"https://doi.org/10.1109/ats.1998.741646","title":"Verification of asynchronous circuits with bounded inertial gate delays","display_name":"Verification of asynchronous circuits with bounded inertial gate delays","publication_year":2002,"publication_date":"2002-11-27","ids":{"openalex":"https://openalex.org/W2154185188","doi":"https://doi.org/10.1109/ats.1998.741646","mag":"2154185188"},"language":"en","primary_location":{"id":"doi:10.1109/ats.1998.741646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.1998.741646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018643965","display_name":"Jie Gong","orcid":"https://orcid.org/0000-0002-9670-6336"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"J. Gong","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113434903","display_name":"E.M.C. Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"E.M.C. Wong","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"399","last_page":"401"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8506747484207153},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7347489595413208},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7329886555671692},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7044931650161743},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.5819623470306396},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5492774844169617},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5172331929206848},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47637316584587097},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4384787380695343},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3207683265209198},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.27835240960121155},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.19478970766067505},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18424436450004578},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13856816291809082},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10923945903778076},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0844486653804779}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8506747484207153},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7347489595413208},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7329886555671692},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7044931650161743},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.5819623470306396},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5492774844169617},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5172331929206848},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47637316584587097},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4384787380695343},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3207683265209198},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.27835240960121155},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.19478970766067505},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18424436450004578},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13856816291809082},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10923945903778076},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0844486653804779},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats.1998.741646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.1998.741646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1534774275","https://openalex.org/W1925866415","https://openalex.org/W4235222319"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W2093992207","https://openalex.org/W2085028021","https://openalex.org/W3094139610","https://openalex.org/W2146990170","https://openalex.org/W2129978639","https://openalex.org/W304800142","https://openalex.org/W2388325543","https://openalex.org/W1993985975","https://openalex.org/W2035720669"],"abstract_inverted_index":{"Verifying":[0],"the":[1,9,17,20,24,33,48,58,63,76],"correctness":[2],"of":[3,8,19,26,50,53,78],"asynchronous":[4,14,30,55],"circuits":[5,31],"is":[6,65,70],"one":[7],"most":[10],"important":[11],"task":[12],"in":[13,29,72],"design.":[15],"However,":[16],"absence":[18],"global":[21],"clock":[22],"and":[23],"variation":[25],"gate":[27],"delays":[28],"makes":[32],"verification":[34,42],"a":[35,41],"formidable":[36],"task.":[37],"In":[38],"this":[39],"paper,":[40],"method":[43],"which":[44],"can":[45],"cover":[46],"all":[47],"deviation":[49],"gate-level":[51],"implementation":[52],"an":[54],"circuit":[56],"from":[57],"specified":[59],"behavior":[60],"given":[61],"by":[62],"STG":[64],"proposed.":[66],"The":[67],"ternary":[68],"logic":[69],"used":[71],"order":[73],"to":[74],"describe":[75],"behaviors":[77],"gates":[79],"with":[80],"bounded":[81],"inertial":[82],"delays.":[83]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}