{"id":"https://openalex.org/W2106203961","doi":"https://doi.org/10.1109/ats.2004.12","title":"A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits","display_name":"A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits","publication_year":2005,"publication_date":"2005-04-06","ids":{"openalex":"https://openalex.org/W2106203961","doi":"https://doi.org/10.1109/ats.2004.12","mag":"2106203961"},"language":"en","primary_location":{"id":"doi:10.1109/ats.2004.12","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2004.12","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th Asian Test Symposium","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073117174","display_name":"Sheng Xu","orcid":"https://orcid.org/0000-0001-8485-3753"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shiy Xu","raw_affiliation_strings":["Shanghai University, Shanghai, China","Shanghai Univ. (China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]},{"raw_affiliation_string":"Shanghai Univ. (China)","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072141048","display_name":"E.A.T.A. Edirisuriya","orcid":null},"institutions":[{"id":"https://openalex.org/I172828483","display_name":"University of Sri Jayewardenepura","ror":"https://ror.org/02rm76t37","country_code":"LK","type":"education","lineage":["https://openalex.org/I172828483"]}],"countries":["LK"],"is_corresponding":false,"raw_author_name":"E. Edirisuriya","raw_affiliation_strings":["University of Sri Jayewardenepura, Nugegoda, Sri Lanka","University of Sri- Jayewardenepura"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Sri Jayewardenepura, Nugegoda, Sri Lanka","institution_ids":["https://openalex.org/I172828483"]},{"raw_affiliation_string":"University of Sri- Jayewardenepura","institution_ids":["https://openalex.org/I172828483"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5834115147590637},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5431874990463257},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.500119686126709},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3894381523132324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36959123611450195},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33963295817375183},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.27807295322418213},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11896812915802002},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11546963453292847}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5834115147590637},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5431874990463257},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.500119686126709},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3894381523132324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36959123611450195},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33963295817375183},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.27807295322418213},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11896812915802002},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11546963453292847}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats.2004.12","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2004.12","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th Asian Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W119550237","https://openalex.org/W165932379","https://openalex.org/W1664574281","https://openalex.org/W2062746030","https://openalex.org/W2074985862","https://openalex.org/W2083177010","https://openalex.org/W2162256736","https://openalex.org/W2180619841","https://openalex.org/W4230203075","https://openalex.org/W4234199418","https://openalex.org/W4249930981","https://openalex.org/W6604907742","https://openalex.org/W6606861424","https://openalex.org/W6637261059"],"related_works":["https://openalex.org/W1604898313","https://openalex.org/W2117014006","https://openalex.org/W4233815414","https://openalex.org/W2372170743","https://openalex.org/W1491899005","https://openalex.org/W2790489068","https://openalex.org/W1558545464","https://openalex.org/W2163661095","https://openalex.org/W2108073943","https://openalex.org/W1940573008"],"abstract_inverted_index":{"Reconvergent":[0],"fanout":[1,32,59,90],"has":[2],"been":[3],"one":[4],"of":[5,11,30,71,86],"the":[6,45,51,57,79],"critical":[7],"issues":[8],"for":[9,16,77],"testing":[10],"VLSI":[12],"circuits":[13,87],"and":[14,54],"design":[15],"testability.":[17],"In":[18],"this":[19],"paper":[20],"we":[21],"present":[22],"a":[23,37],"new":[24],"algorithm,":[25],"which":[26,48],"detects":[27],"all":[28,44,56],"sources":[29],"reconvergent":[31,52,58,64],"branch":[33,60],"pairs":[34,61],"by":[35],"processing":[36],"normal":[38],"circuit":[39],"description.":[40],"The":[41,68],"algorithm":[42],"identifies":[43],"gates":[46],"at":[47,65],"reconvergence":[49,73],"occurs,":[50],"sites,":[53],"lists":[55],"that":[62],"are":[63],"these":[66],"sites.":[67],"automatic":[69],"detection":[70],"such":[72,89],"can":[74],"be":[75],"used":[76],"improving":[78],"testability":[80],"analysis":[81],"or":[82],"assist":[83],"test":[84],"generation":[85],"containing":[88],"branches.":[91]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}