{"id":"https://openalex.org/W2139980821","doi":"https://doi.org/10.1109/ats.2004.20","title":"Adding Testability to an Asynchronous Interconnect for GALS SoC","display_name":"Adding Testability to an Asynchronous Interconnect for GALS SoC","publication_year":2005,"publication_date":"2005-04-06","ids":{"openalex":"https://openalex.org/W2139980821","doi":"https://doi.org/10.1109/ats.2004.20","mag":"2139980821"},"language":"en","primary_location":{"id":"doi:10.1109/ats.2004.20","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2004.20","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th Asian Test Symposium","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039317978","display_name":"Aristides Efthymiou","orcid":"https://orcid.org/0000-0002-2472-982X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Efthymiou","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027781767","display_name":"John Bainbridge","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J. Bainbridge","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108435403","display_name":"D. Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D.A. Edwards","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., Oxford Road, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"20","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8770215511322021},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.757659375667572},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7474719285964966},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6853498220443726},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6340665817260742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5742411017417908},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5093511343002319},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4796588718891144},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45407330989837646},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.42597225308418274},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40984344482421875},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23504957556724548},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.17171382904052734},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.12371483445167542},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12185505032539368},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08116433024406433}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8770215511322021},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.757659375667572},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7474719285964966},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6853498220443726},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6340665817260742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5742411017417908},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5093511343002319},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4796588718891144},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45407330989837646},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.42597225308418274},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40984344482421875},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23504957556724548},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.17171382904052734},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.12371483445167542},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12185505032539368},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08116433024406433},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ats.2004.20","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats.2004.20","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th Asian Test Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/2db3b550-b3b9-457c-8185-2ee73421cc4e","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/2db3b550-b3b9-457c-8185-2ee73421cc4e","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Efthymiou, A, Bainbridge, J & Edwards, D A 2004, Adding testability to an asynchronous interconnect for GALS SoC. in Proceedings of the Asian Test Symposium|Proc Asian Test Symp. IEEE Computer Society , pp. 20-23, Proceedings of the Asian Test Symposium, ATS'04, Kenting, 1/07/04. < http://dblp.uni-trier.de/db/conf/ats/ats2004.html#EfthymiouBE04 >","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/2db3b550-b3b9-457c-8185-2ee73421cc4e","is_oa":false,"landing_page_url":"http://dblp.uni-trier.de/rec/bibtex/conf/ats/EfthymiouBE04.xml","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Efthymiou, A, Bainbridge, J & Edwards, D A 2004, Adding testability to an asynchronous interconnect for GALS SoC. in Proceedings of the Asian Test Symposium|Proc Asian Test Symp. IEEE Computer Society , pp. 20-23, Proceedings of the Asian Test Symposium, ATS'04, Kenting, 1/07/04. < http://dblp.uni-trier.de/db/conf/ats/ats2004.html#EfthymiouBE04 >","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2031273683","https://openalex.org/W2110477287","https://openalex.org/W2126951324"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W4249526199","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2142405811","https://openalex.org/W1589327193"],"abstract_inverted_index":{"Asynchronous":[0],"circuits":[1],"offer":[2],"great":[3],"potential":[4],"for":[5,28],"solving":[6],"the":[7,52,73,76,89],"interconnect":[8,55],"problems":[9],"faced":[10],"by":[11,21,67],"system-on-chip":[12],"designers,":[13],"but":[14],"their":[15],"adoption":[16],"has":[17],"been":[18],"held":[19],"back":[20],"a":[22,40,46,68],"lack":[23],"of":[24,31,49,75,91],"methodology":[25],"and":[26],"support":[27],"fabrication":[29],"testing":[30],"such":[32],"circuits.":[33],"This":[34],"paper":[35],"addresses":[36],"this":[37],"problem":[38],"using":[39],"partial":[41],"scan":[42],"approach":[43],"which":[44,57],"achieves":[45],"test":[47],"coverage":[48],"99.5%":[50],"on":[51],"CHAIN":[53],"network-on-chip":[54],"fabric":[56],"is":[58],"used":[59],"as":[60],"an":[61],"example.":[62],"Test":[63],"patterns":[64],"are":[65,93],"generated":[66],"custom":[69],"program":[70],"automatically,":[71],"given":[72],"topology":[74],"interconnect.":[77],"In":[78],"comparison":[79],"to":[80],"standard,":[81],"asynchronous,":[82],"full-scan":[83],"LSSD":[84],"methods,":[85],"area":[86],"savings":[87],"in":[88],"order":[90],"50%":[92],"noted.":[94]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
