{"id":"https://openalex.org/W2096041455","doi":"https://doi.org/10.1109/eurmic.1999.794493","title":"Technology driven multilevel logic synthesis based on functional decomposition into gates","display_name":"Technology driven multilevel logic synthesis based on functional decomposition into gates","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W2096041455","doi":"https://doi.org/10.1109/eurmic.1999.794493","mag":"2096041455"},"language":"en","primary_location":{"id":"doi:10.1109/eurmic.1999.794493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurmic.1999.794493","pdf_url":null,"source":{"id":"https://openalex.org/S4306523317","display_name":"Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083662315","display_name":"R. Rzechowski","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"R. Rzechowski","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109220541","display_name":"L. J\u00f3\u017awiak","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"L. Jozwiak","raw_affiliation_strings":["Section of Digital Information Systems EH 10.25, Eindhovan University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Section of Digital Information Systems EH 10.25, Eindhovan University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051919904","display_name":"Tadeusz \u0141uba","orcid":"https://orcid.org/0000-0002-4965-7842"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"T. Luba","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":null,"first_page":"368","last_page":"375 vol.1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.7655938863754272},{"id":"https://openalex.org/keywords/functional-decomposition","display_name":"Functional decomposition","score":0.7493613362312317},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6804853677749634},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.63044673204422},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5687828660011292},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5523161888122559},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5496059060096741},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5153505206108093},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4774216413497925},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3922238349914551},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3714650273323059},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28317469358444214},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1516716182231903}],"concepts":[{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.7655938863754272},{"id":"https://openalex.org/C12145135","wikidata":"https://www.wikidata.org/wiki/Q5215396","display_name":"Functional decomposition","level":2,"score":0.7493613362312317},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6804853677749634},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.63044673204422},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5687828660011292},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5523161888122559},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5496059060096741},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5153505206108093},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4774216413497925},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3922238349914551},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3714650273323059},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28317469358444214},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1516716182231903},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1109/eurmic.1999.794493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurmic.1999.794493","pdf_url":null,"source":{"id":"https://openalex.org/S4306523317","display_name":"Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium","raw_type":"proceedings-article"},{"id":"pmh:919517","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=919517","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:library.tue.nl:919517","is_oa":false,"landing_page_url":"http://repository.tue.nl/919517","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/6207242a-f358-4acb-846e-108631b891eb","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/6207242a-f358-4acb-846e-108631b891eb","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Rzechowski, R, Jozwiak, L & Luba, T 1999, Technology driven multilevel logic synthesis based on functional decomposition into gates. in Proceedings - 25th EUROMICRO Conference on Informatics : Theory and Practice for the New Millennium, EUROMICRO 1999., 794493, Institute of Electrical and Electronics Engineers, pp. 368-375, 25th EUROMICRO Conference on Informatics: Theory and Practice for the New Millennium, EUROMICRO 1999, Milan, Italy, 8/09/99. https://doi.org/10.1109/EURMIC.1999.794493","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.tue.nl:publications/6207242a-f358-4acb-846e-108631b891eb","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=13944254278&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Rzechowski, R, Jozwiak, L & Luba, T 1999, Technology driven multilevel logic synthesis based on functional decomposition into gates. in Proceedings - 25th EUROMICRO Conference on Informatics : Theory and Practice for the New Millennium, EUROMICRO 1999., 794493, Institute of Electrical and Electronics Engineers, pp. 368-375, 25th EUROMICRO Conference on Informatics: Theory and Practice for the New Millennium, EUROMICRO 1999, Milan, Italy, 8/09/99. https://doi.org/10.1109/EURMIC.1999.794493","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:tue:oai:pure.tue.nl:publications/6207242a-f358-4acb-846e-108631b891eb","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/6207242a-f358-4acb-846e-108631b891eb","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - 25th EUROMICRO Conference on Informatics: Theory and Practice for the New Millennium, EUROMICRO 1999, 368 - 375","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1579750695","https://openalex.org/W1622626486","https://openalex.org/W1967845326","https://openalex.org/W1978998136","https://openalex.org/W1985663731","https://openalex.org/W2036887642","https://openalex.org/W2069533828","https://openalex.org/W2080019815","https://openalex.org/W2105715355","https://openalex.org/W2110619112","https://openalex.org/W2110997035","https://openalex.org/W2156366819","https://openalex.org/W2160903885","https://openalex.org/W2539416049","https://openalex.org/W2544151355","https://openalex.org/W3144332406","https://openalex.org/W3148005990","https://openalex.org/W4241671559","https://openalex.org/W4250629825"],"related_works":["https://openalex.org/W2125631309","https://openalex.org/W1980308745","https://openalex.org/W2078452800","https://openalex.org/W2147890927","https://openalex.org/W2053477566","https://openalex.org/W2120569261","https://openalex.org/W3143008962","https://openalex.org/W2100921984","https://openalex.org/W1966574477","https://openalex.org/W2402143345"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"a":[3,39],"new":[4],"method":[5],"is":[6,70],"proposed":[7],"for":[8,73],"multilevel":[9],"logic":[10],"synthesis":[11],"based":[12],"on":[13],"functional":[14,52,62],"decomposition":[15,31,63],"into":[16],"gates.":[17],"Unlike":[18],"the":[19,23,26,30,34,51,65],"traditional":[20,60],"approach":[21,55],"to":[22,58],"decomposition,":[24],"where":[25],"basic":[27],"components":[28],"of":[29,43,50],"network":[32],"are":[33],"universal":[35],"cells,":[36],"we":[37],"propose":[38],"method,":[40],"which":[41,69],"instead":[42],"cells":[44],"uses":[45],"gates,":[46],"but":[47],"preserves":[48],"advantages":[49],"decomposition.":[53],"This":[54],"makes":[56],"possible":[57],"improve":[59],"FPGA":[61],"onto":[64],"more":[66],"general":[67],"algorithm,":[68],"also":[71],"useful":[72],"other":[74],"technologies":[75],"in":[76],"VLSI":[77],"ASIC":[78],"design.":[79]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
