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ORCID32nd SoCC 2019: Singapore
- 32nd IEEE International System-on-Chip Conference, SOCC 2019, Singapore, September 3-6, 2019. IEEE 2019, ISBN 978-1-7281-3483-3
- Ram K. Krishnamurthy:
Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities. 1-3 - Yu Huang, Rahul Singhal:
Tutorial 1B: AI Chip Technologies and DFT Methodologies. 1-2 - Norbert Wehn:
Wednesday Keynote: The Memory Wall: Challenges and Solutions. 1-2 - Massimo Alioto:
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling. 1-3 - Ahmed Abelgawad:
Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research. 1-2 - Jerome Tija:
Thursday Plenary: Anchoring Security in the Connected World. 1-3 - Tan-Tan Zhang
, Yuan Gao:
A BJT-Based Temperature Sensor in 40-nm CMOS With ±0.8°C(3σ) Untrimmed Inaccuracy. 1-4 - Manoj Sachdev:
Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test. 1-2 - Tony Tae-Hyoung Kim:
Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory. 1-2 - Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor:
A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications. 5-10 - Ata Khorami, Manoj Sachdev, Mohammad Sharifkhani:
A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications. 11-16 - Xiaoyu Guo, Hongge Li:
A 10-bit Area-efficient Source Driver for Printed OLED Display. 17-20 - Sidhartha Sankar Rout, Vaibhav Ishwarlal Chaudhari, Suyog Bhimrao Patil, Sujay Deb:
RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC. 21-26 - Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do:
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. 27-32 - Seungseok Nam, Emil Matús, Gerhard P. Fettweis:
Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs. 33-38 - Fabian Kempf, Nidhi Anantharajaiah, Leonard Masing, Jürgen Becker:
A Network on Chip Adapter for Real-Time and Safety-Critical Applications. 39-44 - Yu Zheng, Yongxin Zhu, Yuefeng Song, Tianhao Nan, Wanyi Li:
A Lossless Astronomical Data Compression Scheme with FPGA Acceleration. 45-49 - Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao:
An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform. 50-55 - Weixiong Jiang, Heng Yu, Yajun Ha:
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC. 56-61 - Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. 62-67 - Zhuo Chen, Yuqian Pan, Mingyang Gong, Haichun Zhang, Mingyu Zhang, Zhenglin Liu:
A NAND Flash Endurance Prediction Scheme with FPGA-based Memory Controller System. 68-73 - De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
A Glitch Key-Gate for Logic Locking. 74-79 - Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen:
A Novel Test Vector Generation Method for Hardware Trojan Detection. 80-85 - Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee:
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. 86-91 - Guan-Min Luo, Ching-Yuan Yang:
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection. 92-96 - Patricia Gonzalez-Guerrero, Stephen G. Wilson, Mircea R. Stan:
Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT. 97-102 - Ming Ming Wong, Anh-Tuan Do:
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. 103-108 - Ching-Che Chung, Hsin-Han Huang:
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications. 109-112 - Wei-Chien Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation. 113-117 - Jiun-In Guo, Chia-Chi Tsai, Ching-Kan Tseng:
Pvalite CLN: Lightweight Object Detection with Classfication and Localization Network. 118-121 - Zhongyuan Fang, Liheng Lou, Kai Tang, Ting Guo, Bo Chen, Yisheng Wang, Chuanshi Yang, Longjie Zhong, Yuanjin Zheng:
A Digital-Enhanced Interferometric Radar Sensor for Physiological Sign Monitoring. 122-125 - Naveed Mahmud, Esam El-Araby:
Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms. 126-131 - Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima:
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. 132-137 - Chong Yeam Tan, Chia Yee Ooi, Nordinah Ismail:
Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis. 138-143 - Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran:
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks. 144-149 - Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. 150-154 - Jiquan Li, Yingmei Chen, Zhen Zhang, Hui Wang, Chao Guo, Binbin Yang:
Group Delay Compensation By Combining 3-tap FFE With CTLE for 80Gbps-PAM4 Optical Transmitter. 155-160 - Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine:
Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. 161-164 - Hui Wang, Yingmei Chen, Yuan Gao, Ning Li, Zhen Zhang, Chao Guo, Jiquan Li:
A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18 μm SiGe BiCMOS Technology. 165-170 - Ke Xu, Fang Zhu, Hong Wang, Xiao Zhang, Bin Han, Jiewei Xiao, Dehui Kong, Zhou Han, Degen Zhen, Guoning Lu, Jisong Ai, Xin Liu, Zhi Huang:
A 4K Vision Computing Platform with Convolutional Neural Network Engine on FPGA. 171-175 - Yibo Fan, Jiro Katto, Heming Sun, Xiaoyang Zeng, Yixuan Zeng:
A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard. 176-180 - Bo Wang, Jiayan Gan, Yuxiang Xie, Yin Wang, Zhuoling Xiao, Jun Zhou:
A Power-Efficient Programmable DCNN Processor for Intelligent Sensing. 181-186 - Fengwei An, Peng Xu, Zhihua Xiao, Chao Wang:
FPGA-based object detection processor with HOG feature and SVM classifier. 187-190 - S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
Efficient Hardware Acceleration of Convolutional Neural Networks. 191-192 - Debanjana Datta, Baidyanath Ray, Ayan Banerjee:
Synthesis of Linear and Non-linear Analog Circuits. 193-194 - Matthew Hagan, Sakir Sezer, Kieran McLaughlin:
Reactive and Proactive Threat Detection and Prevention for the Internet of Things. 195-196 - Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. 197-202 - Florian Oszwald, Philipp Obergfell, Matthias Traub, Jürgen Becker:
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration. 203-208 - Yunfeng Hu, Lisheng Chen, Hui Chen, Yi Wen, Huabin Zhang, Xiaojia Liu:
A 100 KS/s 8-10 bit resolution-reconfigurable SAR ADC for bioelectronics application. 209-212 - Yi Jin, Jiawei Xu, Yuxiang Huan, Yulong Yan, Lirong Zheng, Zhuo Zou:
Energy-Aware Workload Allocation for Distributed Deep Neural Networks in Edge-Cloud Continuum. 213-217 - Fahad Siddiqui, Matthew Hagan, Sakir Sezer:
Establishing Cyber Resilience in Embedded Systems for Securing Next-Generation Critical Infrastructure. 218-223 - Sai Praveen Kadiyala, Vikram Kumar Pudi, Mohit Garg, Hau T. Ngo, Siew-Kei Lam, Thambipillai Srikanthan:
Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images. 224-229 - Sidhartha Sankar Rout, Suyog Bhimrao Patil, Vaibhav Ishwarlal Chaudhari, Sujay Deb:
Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation. 230-235 - Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. 236-241 - Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do:
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. 242-247 - Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. 248-253 - Debjyoti Bhattacharjee, Anupam Chattopadhyay, Ricardo Jack Liwongan:
Accelerating Binary-Matrix Multiplication on FPGA. 254-259 - Vishnu Asutosh Dasu, Anubhab Baksi, Sumanta Sarkar, Anupam Chattopadhyay:
LIGHTER-R: Optimized Reversible Circuit Implementation For SBoxes. 260-265 - Luka Daoud, Nader Rafla:
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. 266-271 - Kasem Khalil, Omar Eldash, Ashok Kumar, Magdy A. Bayoumi:
N2 OC: Neural-Network-on-Chip Architecture. 272-277 - Tobias Schirmer, Mohammad Mahdi Khafaji, Jan Plíva, Frank Ellinger:
A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment. 278-283 - You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang:
A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. 284-288 - Sotoudeh Hamedi-Hagh:
Analysis and Modeling of Passive LC Filters Using Node Elimination Technique. 289-293 - Johannes Pfau, Maximilian Reuter, Tanja Harbaum, Klaus Hofmann, Jürgen Becker:
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s. 294-299 - Server Kasap, Soydan Redif, Eduardo Wächter:
Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip. 300-305 - Hirotoshi Ito, Minoru Watanabe:
Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array. 306-311 - Anh-Tuan Do:
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique. 312-317 - Jyotibdha Acharya, Andrés Ussa Caycedo, Vandana Reddy Padala, Rishi Raj Sidhu Singh, Garrick Orchard, Bharath Ramesh, Arindam Basu:
EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT using Stationary Neuromorphic Vision Sensors. 318-323 - Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen:
An Efficient Implementation of Arbiter PUF on FPGA for IoT Application. 324-329 - Yi Guo, Heming Sun, Shinji Kimura:
Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors. 330-335 - Nguyen Van Toan, Jeong-Gun Lee:
Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs. 336-341 - Alberto Nannarelli:
Fused Multiply-Add for Variable Precision Floating-Point. 342-347 - Kejie Huang, Chuyun Qin:
eNVM based In-memory Computing for Intelligent and Secure Computing Systems. 348-353 - Weijie Wang, Victor Yi-Qian Zhuo, Zhixian Chen, Hock Koon Lee, Minghua Li, Wendong Song:
Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance. 354-358 - Fei Li, Jayce Lay Keng Lim:
ReRAM Non-Volatile AES Encryption Engine for IoT Application. 359-364 - Victor Yi-Qian Zhuo, Weijie Wang, Zhixian Chen, Hock Koon Lee, Minghua Li, Wendong Song:
Co-Design of Highly Uniform ReRAM Arrays in 180nm CMOS Technology for Neuromorphic Systems. 365-369 - Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez:
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. 370-375 - H. T. Manohara, B. P. Harish:
Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming. 376-381 - David Akselrod:
ML-based Reinforcement Learning Approach for Power Management in SoCs. 382-387 - Kasem Khalil, Omar Eldash, Ashok Kumar, Magdy A. Bayoumi:
A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration. 388-393 - Rahul Dutta, Salahuddin Raju, Ashish James, Leo John Chemmanda, Yong-Joon Jeon, Balagopal Unnikrishnan, Chuan Sheng Foo, Zeng Zeng, Kevin Tshun Chuan Chai, Vijay Ramaseshan Chandrasekhar:
Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN). 394-399 - Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang:
Crosstalk-aware TSV-buffer Insertion in 3D IC. 400-405 - Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Poças, Thomas Wild, Andreas Herkersdorf:
Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. 406-411 - Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. 412-417 - Vinay B. Y. Kumar, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson:
ITUS: A Secure RISC-V System-on-Chip. 418-423 - Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
Protecting the Integrity of Processor Cores with Logic Encryption. 424-425 - Avi Mendelson:
Secure Speculative Core. 426-431 - Gnanambikai Krishnakumar, Chester Rebeiro:
MSMPX: Microarchitectural Extensions for Meltdown Safe Memory Protection. 432-437 - Kuhwa sung, Terng-Yin Hsu:
Scalable DU Architecture for IoT massive connection. 438-443 - Huiliang Zhang, Zhonglong Wang, Fei Qin, Meng Ma, Jianhua Zhang:
A Neural-Network-Based Non-linear Interference Cancellation Scheme for Wireless IoT Backhaul with Dual-Connectivity. 444-448 - Hsiang-Ming Yen, Chia-Ling Wei, Chi-Shi Chen, Terng-Yin Hsu:
High-Efficiency Step-Down Multi-Mode Switching DC-DC Converter for IoT Devices. 449-454 - Debanjana Datta, Mousumi Bhanja, Anirban Chaudhuri, Baidyanath Ray, Ayan Banerjee:
Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits. 455-460 - Sreekesh Lakshminarayanan, Klaus Hofmann:
A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications. 461-465 - Wei Zhou, Wang Ling Goh, Yi Chen, Tantan Zhang, Yuan Gao:
A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-nm CMOS. 466-470 - Liheng Tang, Kai Tang, Zhongyuan Fang, Yisheng Wang, Bo Chen, Ting Guo, Chuanshi Yang, Yuanjin Zheng:
Radar Transceivers for Inverse Synthetic Aperture Radar (ISAR) Imaging of Human Activity in 65nm CMOS. 471-474 - Bongjin Kim:
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks. 475-478 - Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha:
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design. 479-483 - Chuanshi Yang, Kai Tang, Lei Qiu, Zhongyuan Fang, Yuanjin Zheng:
A Low Power Analog Front-end for Ultrasound Receiver. 484-487 - Wen-Cheng Lai, Sheng-Lyang Jang:
Current-Reuse LC Divide-by-8 Injection-Locked Frequency Divider. 488-491
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