Beyond SPICE.

Ibrahim N. Hajj Ibrahim N. Hajj Beyond SPICE. 1 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050857 conf/iscas/2017 db/conf/iscas/iscas2017.html#Hajj17

Ibrahim N. Hajj On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors. 495-499 2015 34 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2014.2387864 db/journals/tcad/tcad34.html#Hajj15

Ibrahim N. Hajj Extended Nodal Analysis. 89-100 2012 31 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/TCAD.2011.2167330 db/journals/tcad/tcad31.html#Hajj12

Murat R. Becer David T. Blaauw Ilan Algor Rajendran Panda Chanhee Oh Vladimir Zolotov Ibrahim N. Hajj Postroute gate sizing for crosstalk noise reduction. 1670-1677 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2004.836736 db/journals/tcad/tcad23.html#BecerBAPOZH04

Murat R. Becer David T. Blaauw Rajendran Panda Ibrahim N. Hajj Early probabilistic noise estimation for capacitively coupled interconnects. 337-345 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2002.807892 db/journals/tcad/tcad22.html#BecerBPH03

Murat R. Becer David T. Blaauw Ilan Algor Rajendran Panda Chanhee Oh Vladimir Zolotov Ibrahim N. Hajj Post-route gate sizing for crosstalk noise reduction. 954-957 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.776071 db/conf/dac/dac2003.html#BecerBAPOZH03 Murat R. Becer David T. Blaauw Ilan Algor Rajendran Panda Chanhee Oh Vladimir Zolotov Ibrahim N. Hajj Post-Route Gate Sizing for Crosstalk Noise Reduction. 171-176 2003 conf/isqed/2003 ISQED https://doi.org/10.1109/ISQED.2003.1194727 https://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194727 db/conf/isqed/isqed2003.html#BecerBAPOZH03

Vikram Saxena Farid N. Najm Ibrahim N. Hajj Estimation of state line statistics in sequential circuits. 455-473 2002 7 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/567270.567275 db/journals/todaes/todaes7.html#SaxenaNH02

Sumant Ramprasad Ibrahim N. Hajj Farid N. Najm A technique for Improving dual-output domino logic. 508-511 2002 10 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2002.800521 db/journals/tvlsi/tvlsi10.html#RamprasadHN02

Murat R. Becer Vladimir Zolotov David T. Blaauw Rajendran Panda Ibrahim N. Hajj Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . 456-463 2002 conf/date/2002 DATE https://doi.org/10.1109/DATE.2002.998313 https://doi.ieeecomputersociety.org/10.1109/DATE.2002.998313 http://dl.acm.org/citation.cfm?id=874413 db/conf/date/date2002.html#BecerZBPH02 Geng Bai Ibrahim N. Hajj Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. 163-168 2002 conf/isqed/2002 ISQED https://doi.org/10.1109/ISQED.2002.996723 db/conf/isqed/isqed2002.html#BaiH02 Murat R. Becer Rajendran Panda David T. Blaauw Ibrahim N. Hajj Pre-route Noise Estimation in Deep Submicron Integrated Circuits. 413-418 2002 conf/isqed/2002 ISQED https://doi.org/10.1109/ISQED.2002.996781 https://doi.ieeecomputersociety.org/10.1109/ISQED.2002.996781 db/conf/isqed/isqed2002.html#BecerPBH02 Murat R. Becer David T. Blaauw Ibrahim N. Hajj Rajendran Panda Early probabilistic noise estimation for capacitively coupled interconnects. 77-83 2002 conf/slip/2002 SLIP https://doi.org/10.1145/505348.505365 db/conf/slip/slip2002.html#BecerBHP02 Geng Bai Sudhakar Bobba Ibrahim N. Hajj Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. 295-300 2001 conf/dac/2001 DAC https://doi.org/10.1145/378239.378489 db/conf/dac/dac2001.html#BaiBH01 Geng Bai Sudhakar Bobba Ibrahim N. Hajj Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms. 1437-1440 2001 ICECS https://doi.org/10.1109/ICECS.2001.957485 conf/icecsys/2001 db/conf/icecsys/icecsys2001.html#BaiBH01 Sudhakar Bobba Ibrahim N. Hajj Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. 195-198 2001 conf/iscas/2001 ISCAS (5) https://doi.org/10.1109/ISCAS.2001.922018 db/conf/iscas/iscas2001-5.html#BobbaH01 Sudhakar Bobba Ibrahim N. Hajj Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. 376-381 2001 conf/islped/2001 ISLPED https://doi.org/10.1145/383082.383186 db/conf/islped/islped2001.html#BobbaH01 Ninglong Lu Ibrahim N. Hajj A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. 133-138 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915217 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915217 db/conf/isqed/isqed2001.html#LuH01 Murat R. Becer David T. Blaauw Supamas Sirichotiyakul Chanhee Oh Vladimir Zolotov Jingyan Zuo Rafi Levy Ibrahim N. Hajj A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. 158-163 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915221 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915221 db/conf/isqed/isqed2001.html#BecerBSOZZLH01 Geng Bai Sudhakar Bobba Ibrahim N. Hajj RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 205-210 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915228 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915228 db/conf/isqed/isqed2001.html#BaiBH01 Geng Bai Sudhakar Bobba Ibrahim N. Hajj RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 257-258 2001 conf/isqed/2001 ISQED https://doi.org/10.1109/ISQED.2001.915238 https://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915238 db/conf/isqed/isqed2001.html#BaiBH01a

Nikolaos Bellas Ibrahim N. Hajj Constantine D. Polychronopoulos George I. Stamoulis Architectural and compiler techniques for energy reduction in high-performance microprocessors. 317-326 2000 8 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/92.845897 https://www.wikidata.org/entity/Q123154646 db/journals/tvlsi/tvlsi8.html#BellasHPS00

Nikolaos Bellas Ibrahim N. Hajj Constantine D. Polychronopoulos Using dynamic cache management techniques to reduce energy in general purpose processors. 693-708 2000 8 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/92.902264 db/journals/tvlsi/tvlsi8.html#BellasHP00

Sudhakar Bobba Ibrahim N. Hajj High-performance bidirectional repeaters. 53-58 2000 conf/glvlsi/2000 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/330855.330964 db/conf/glvlsi/glvlsi2000.html#BobbaH00 Sudhakar Bobba Ibrahim N. Hajj Peak current estimation for digital filters. 3251-3254 2000 ICASSP https://doi.org/10.1109/ICASSP.2000.860093 https://doi.ieeecomputersociety.org/10.1109/ICASSP.2000.860093 conf/icassp/2000 db/conf/icassp/icassp2000.html#BobbaH00 Geng Bai Sudhakar Bobba Ibrahim N. Hajj Simulation and Optimization of the Power Distribution Network in VLSI Circuits. 481-486 2000 conf/iccad/2000 ICCAD db/conf/iccad/iccad2000.html#BaiBH00 https://doi.org/10.1109/ICCAD.2000.896519 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2000.896519 http://dl.acm.org/citation.cfm?id=603011 Sudhakar Bobba Ibrahim N. Hajj Current-Mode Threshold Logic Gates. 235-240 2000 conf/iccd/2000 ICCD https://doi.org/10.1109/ICCD.2000.878291 https://doi.ieeecomputersociety.org/10.1109/ICCD.2000.878291 db/conf/iccd/iccd2000.html#BobbaH00 Mohammad M. Mansour Makram M. Mansour Ibrahim N. Hajj Naresh R. Shanbhag Instruction scheduling for low power on dynamically variable voltage processors. 613-618 2000 ICECS https://doi.org/10.1109/ICECS.2000.911614 conf/icecsys/2000 db/conf/icecsys/icecsys2000.html#MansourMHS00 Murat R. Becer Ibrahim N. Hajj An analytical model for delay and crosstalk estimation in interconnects under general switching conditions. 831-834 2000 ICECS https://doi.org/10.1109/ICECS.2000.913005 conf/icecsys/2000 db/conf/icecsys/icecsys2000.html#BecerH00 Ninglong Lu Ibrahim N. Hajj A hierarchical based approach for coupling aware delay analysis of combinational logic blocks. 1012-1015 2000 ICECS https://doi.org/10.1109/ICECS.2000.913047 conf/icecsys/2000 db/conf/icecsys/icecsys2000.html#LuH00 Murat R. Becer Ibrahim N. Hajj An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. 51-58 2000 conf/isqed/2000 ISQED https://doi.org/10.1109/ISQED.2000.838853 https://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838853 db/conf/isqed/isqed2000.html#BecerH00 Geng Bai Sudhakar Bobba Ibrahim N. Hajj Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 263-268 2000 conf/isqed/2000 ISQED https://doi.org/10.1109/ISQED.2000.838881 https://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838881 db/conf/isqed/isqed2000.html#BaiBH00

Andreas G. Veneris Ibrahim N. Hajj Design error diagnosis and correction via test vector simulation. 1803-1816 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/43.811329 db/journals/tcad/tcad18.html#VenerisH99

Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj A coding framework for low-power address and data busses. 212-221 1999 7 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.766748 db/journals/tvlsi/tvlsi7.html#RamprasadSH99

Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Information-theoretic bounds on average signal transition activity [VLSI systems]. 359-368 1999 7 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/92.784097 db/journals/tvlsi/tvlsi7.html#RamprasadSH99a

Ninglong Lu Ibrahim N. Hajj An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. 68- 1999 conf/glvlsi/1999 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1999.757379 https://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757379 db/conf/glvlsi/glvlsi1999.html#LuH99 Nikolaos Bellas Ibrahim N. Hajj Constantine D. Polychronopoulos George D. Stamoulis Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. 378-383 1999 conf/iccd/1999 ICCD https://doi.org/10.1109/ICCD.1999.808570 https://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808570 db/conf/iccd/iccd1999.html#BellasHPS99 Andreas G. Veneris Ibrahim N. Hajj A hybrid approach to design error detection and correction [VLSI digital circuits]. 347-350 1999 ICECS https://doi.org/10.1109/ICECS.1999.812294 conf/icecsys/1999 db/conf/icecsys/icecsys1999.html#VenerisH99 Andreas G. Veneris Ibrahim N. Hajj Correcting multiple design errors in digital VLSI circuits. 31-34 1999 conf/iscas/1999 ISCAS (1) https://doi.org/10.1109/ISCAS.1999.777798 db/conf/iscas/iscas1999-1.html#VenerisH99 Nikolaos Bellas Ibrahim N. Hajj Constantine D. Polychronopoulos An analytical, transistor-level energy model for SRAM-based caches. 198-201 1999 conf/iscas/1999 ISCAS (6) https://doi.org/10.1109/ISCAS.1999.780129 db/conf/iscas/iscas1999-6.html#BellasHP99 Ninglong Lu Ibrahim N. Hajj A reduced-order scheme for coupled lumped-distributed interconnect simulation. 250-253 1999 conf/iscas/1999 ISCAS (6) https://doi.org/10.1109/ISCAS.1999.780142 db/conf/iscas/iscas1999-6.html#LuH99 Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Low-power distributed arithmetic architectures using nonuniform memory partitioning. 470-473 1999 conf/iscas/1999 ISCAS (3) https://doi.org/10.1109/ISCAS.1999.778885 db/conf/iscas/iscas1999-3.html#RamprasadSH99 Nikolaos Bellas Ibrahim N. Hajj Constantine D. Polychronopoulos Using dynamic cache management techniques to reduce energy in a high-performance processor. 64-69 1999 conf/islped/1999 ISLPED https://doi.org/10.1145/313817.313856 db/conf/islped/islped1999.html#BellasHP99 Sumant Ramprasad Ibrahim N. Hajj Farid N. Najm An optimization technique for dual-output domino logic. 258-260 1999 conf/islped/1999 ISLPED https://doi.org/10.1145/313817.313939 db/conf/islped/islped1999.html#RamprasadHN99 Sudhakar Bobba Ibrahim N. Hajj Naresh R. Shanbhag Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. 358- 1999 conf/vlsid/1999 VLSI Design https://doi.org/10.1109/ICVD.1999.745182 https://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745182 db/conf/vlsid/vlsid1999.html#BobbaHS99 Andreas G. Veneris Ibrahim N. Hajj Srikanth Venkataraman W. Kent Fuchs Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. 58-63 1999 conf/vts/1999 VTS https://doi.org/10.1109/VTEST.1999.766647 https://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766647 db/conf/vts/vts1999.html#VenerisHVF99 Sudhakar Bobba Ibrahim N. Hajj Maximum Current Estimation in Programmable Logic Arrays. 301-306 1998 conf/glvlsi/1998 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1998.665276 https://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665276 db/conf/glvlsi/glvlsi1998.html#BobbaH98 Nikolaos Bellas Ibrahim N. Hajj George D. Stamoulis Constantine D. Polychronopoulos Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. 70-75 1998 conf/islped/1998 ISLPED https://doi.org/10.1145/280756.280788 https://www.wikidata.org/entity/Q130961939 db/conf/islped/islped1998.html#HajjSBP98 Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Decorrelating (DECOR) transformations for low-power adaptive filters. 250-255 1998 conf/islped/1998 ISLPED https://doi.org/10.1145/280756.280923 db/conf/islped/islped1998.html#RamprasadSH98 Sudhakar Bobba Ibrahim N. Hajj Estimation of maximum current envelope for power bus analysis and design. 141-146 1998 conf/ispd/1998 ISPD https://doi.org/10.1145/274535.274556 db/conf/ispd/ispd1998.html#BobbaH98 Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. 18-23 1998 conf/vlsid/1998 VLSI Design db/conf/vlsid/vlsid1998.html#RamprasadSH98 https://doi.org/10.1109/ICVD.1998.646572 https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646572

Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Analytical estimation of signal transition activity from word-level statistics. 718-733 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/43.644033 db/journals/tcad/tcad16.html#RamprasadSH97

Pi-Yu Chung Ibrahim N. Hajj Diagnosis and correction of multiple logic design errors in digital circuits. 233-237 1997 5 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.585227 db/journals/tvlsi/tvlsi5.html#ChungH97

Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Analytical Estimation of Transition Activity From Word-Level Signal Statistics. 582-587 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266289 db/conf/dac/dac97.html#RamprasadSH97 Vikram Saxena Farid N. Najm Ibrahim N. Hajj Monte-Carlo approach for power estimation in sequential circuits. 416-420 1997 ED&TC https://doi.org/10.1109/EDTC.1997.582393 https://doi.ieeecomputersociety.org/10.1109/EDTC.1997.582393 https://dl.acm.org/doi/10.5555/787260.787697 conf/date/1997 db/conf/date/edtc1997.html#SaxenaNH97 Andreas G. Veneris Ibrahim N. Hajj A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. 45-50 1997 conf/glvlsi/1997 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1997.580409 https://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580409 db/conf/glvlsi/glvlsi1997.html#VenerisH97 Sumant Ramprasad Naresh R. Shanbhag Ibrahim N. Hajj Achievable bounds on signal transition activity. 126-129 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643387 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643387 https://dl.acm.org/citation.cfm?id=266448 db/conf/iccad/iccad1997.html#RamprasadSH97 Tzuhao Chen Ibrahim N. Hajj GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. 555-561 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643594 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643594 https://dl.acm.org/citation.cfm?id=266551 db/conf/iccad/iccad1997.html#ChenH97

Ping-Chung Li Ibrahim N. Hajj Computer-aided redesign of VLSI circuits for hot-carrier reliability. 453-464 1996 15 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.506133 db/journals/tcad/tcad15.html#LiH96

Terry Lee Ibrahim N. Hajj Elizabeth M. Rudnick Janak H. Patel Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. 456-462 1996 conf/vts/1996 VTS https://doi.org/10.1109/VTEST.1996.510893 https://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510893 db/conf/vts/vts1996.html#LeeHRP96

Weitong Chuang Sachin S. Sapatnekar Ibrahim N. Hajj Timing and area optimization for standard-cell VLSI circuit design. 308-320 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.365122 db/journals/tcad/tcad14.html#ChuangSH95

Terry Lee Weitong Chuang Ibrahim N. Hajj W. Kent Fuchs Circuit-level dictionaries of CMOS bridging faults. 596-603 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.384422 db/journals/tcad/tcad14.html#LeeCHF95

Harish Kriplani Farid N. Najm Ibrahim N. Hajj Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. 998-1012 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/43.402499 db/journals/tcad/tcad14.html#KriplaniNH95

Farid N. Najm Shashank Goel Ibrahim N. Hajj Power Estimation in Sequential Circuits. 635-640 1995 conf/dac/1995 DAC https://doi.org/10.1145/217474.217602 db/conf/dac/dac95.html#NajmGH95

Ping-Chung Li Georgios I. Stamoulis Ibrahim N. Hajj A probabilistic timing approach to hot-carrier effect estimation. 1223-1234 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/43.317465 db/journals/tcad/tcad13.html#LiSH94

Pi-Yu Chung Yi-Min Wang Ibrahim N. Hajj Logic design error diagnosis and correction. 320-332 1994 2 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/92.311641 db/journals/tvlsi/tvlsi2.html#ChungWH94

Weitong Chuang Ibrahim N. Hajj Delay and area optimization for compact placement by gate resizing and relocation. 145-148 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629757 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629757 https://dl.acm.org/citation.cfm?id=191385 db/conf/iccad/iccad1994.html#ChuangH94 Harish Kriplani Farid N. Najm Ibrahim N. Hajj Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. 435-438 1994 conf/iscas/1994 ISCAS db/conf/iscas/iscas1994-1.html#KriplaniNH94 https://doi.org/10.1109/ISCAS.1994.408832 Terry Lee Weitong Chuang Ibrahim N. Hajj W. Kent Fuchs Circuit-level dictionaries of CMOS bridging faults. 386-391 1994 VTS https://doi.org/10.1109/VTEST.1994.292284 https://doi.ieeecomputersociety.org/10.1109/VTEST.1994.292284 conf/vts/1994 db/conf/vts/vts1994.html#LeeCHF94

Andrew T. Yang Yu-Hsu Chang Daniel G. Saab Ibrahim N. Hajj Switch-level timing simulation of bipolar ECL circuits. 516-530 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.229735 db/journals/tcad/tcad12.html#YangCSH93

Georgios I. Stamoulis Ibrahim N. Hajj Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. 379-383 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164939 db/conf/dac/dac93.html#StamoulisH93 Harish Kriplani Farid N. Najm Ping Yang 0001 Ibrahim N. Hajj Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. 384-388 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164941 db/conf/dac/dac93.html#KriplaniNYH93 Pi-Yu Chung Yi-Min Wang Ibrahim N. Hajj Diagnosis and Correction of Logic Design Errors in Digital Circuits. 503-508 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.165003 db/conf/dac/dac93.html#ChungWH93 Weitong Chuang Sachin S. Sapatnekar Ibrahim N. Hajj A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. 220-223 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580060 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580060 https://dl.acm.org/citation.cfm?id=259832 db/conf/iccad/iccad1993.html#ChuangSH93 Ping-Chung Li Ibrahim N. Hajj Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability. 534-537 1993 conf/iccd/1993 ICCD db/conf/iccd/iccd1993.html#LiH93 https://doi.org/10.1109/ICCD.1993.393320 https://doi.ieeecomputersociety.org/10.1109/ICCD.1993.393320 Weitong Chuang Ibrahim N. Hajj Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. 1503-1506 1993 conf/iscas/1993 ISCAS db/conf/iscas/iscas1993-3.html#ChuangH93 Pi-Yu Chung Ibrahim N. Hajj Janak H. Patel Efficient Variable Ordering Heuristics for Shared ROBDD. 1690-1693 1993 conf/iscas/1993 ISCAS db/conf/iscas/iscas1993-3.html#ChungHP93 Harish Kriplani Farid N. Najm Ibrahim N. Hajj Maximum Current Estimation in CMOS Circuits. 2-7 1992 conf/dac/1992 DAC http://portal.acm.org/citation.cfm?id=113938.113937 db/conf/dac/dac92.html#KriplaniNH92 Ping-Chung Li Georgios I. Stamoulis Ibrahim N. Hajj A probabilistic timing approach to hot-carrier effect estimation. 210-213 1992 conf/iccad/1992 ICCAD https://doi.org/10.1109/ICCAD.1992.279373 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1992.279373 https://dl.acm.org/citation.cfm?id=304088 db/conf/iccad/iccad1992.html#LiSH92 Pi-Yu Chung Ibrahim N. Hajj ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. 742-751 1992 conf/itc/1992 ITC db/conf/itc/itc1992.html#ChungH92 https://doi.org/10.1109/TEST.1992.527896 https://doi.ieeecomputersociety.org/10.1109/TEST.1992.527896 Ibrahim N. Hajj Terry Lee Simulation of physical faults in VLSI circuits. 202-207 1992 VTS https://doi.org/10.1109/VTEST.1992.232750 https://doi.ieeecomputersociety.org/10.1109/VTEST.1992.232750 conf/vts/1992 db/conf/vts/vts1992.html#HajjL92

Farid N. Najm Ibrahim N. Hajj Ping Yang 0001 An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. 1372-1381 1991 10 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/43.97616 db/journals/tcad/tcad10.html#NajmHY91

Terry Lee Ibrahim N. Hajj A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. 554-557 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#LeeH91 https://doi.org/10.1109/ICCAD.1991.185330 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185330

P. Gee Min-You Wu S. M. Kang Ibrahim N. Hajj A metal - metal matrix cell generator for multi-level metal MOS technology. 25-47 1990 9 Integr. 1 https://doi.org/10.1016/0167-9260(90)90004-K db/journals/integration/integration9.html#GeeWKH90

Ibrahim N. Hajj Stig Skelboe A multilevel parallel solver for block tridiagonal and banded linear systems. 21-45 1990 15 Parallel Comput. 1-3 db/journals/pc/pc15.html#HajjS90 https://doi.org/10.1016/0167-8191(90)90029-9

Farid N. Najm Richard Burch Ping Yang 0001 Ibrahim N. Hajj Probabilistic simulation for reliability analysis of CMOS VLSI circuits. 439-450 1990 9 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.45875 db/journals/tcad/tcad9.html#NajmBYH90

Farid N. Najm Ibrahim N. Hajj The complexity of fault detection in MOS VLSI circuits. 995-1001 1990 9 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.59075 db/journals/tcad/tcad9.html#NajmH90

Ibrahim N. Hajj An Algebra for Switch-Level Simulation. 488-491 1990 conf/iccad/1990 ICCAD db/conf/iccad/iccad1990.html#Hajj90 https://doi.org/10.1109/ICCAD.1990.129961 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1990.129961 Young-Hyun Jun Ibrahim N. Hajj Sang-Heon Lee Song-Bai Park High speed VLSI logic simulation using bitwise operations and parallel processing. 171-174 1990 ICCD https://doi.org/10.1109/ICCD.1990.130193 https://doi.ieeecomputersociety.org/10.1109/ICCD.1990.130193 conf/iccd/1990 db/conf/iccd/iccd1990.html#JunHLP90

Min-You Wu Ibrahim N. Hajj Switching network logic approach to sequential MOS circuit design. 782-794 1989 8 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/43.31535 db/journals/tcad/tcad8.html#WuH89

David Overhauser Ibrahim N. Hajj Yi-Fan Hsu Automatic mixed-mode timing simulation. 84-87 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76910 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76910 conf/iccad/1989 db/conf/iccad/iccad1989.html#OverhauserHH89 P. Gee Ibrahim N. Hajj Sung-Mo Kang A custom cell generation system for double-metal CMOS technology. 140-143 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76922 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76922 conf/iccad/1989 db/conf/iccad/iccad1989.html#GeeHK89 Farid N. Najm Ibrahim N. Hajj Ping Yang 0001 Computation of bus current variance for reliability estimation of VLSI circuits. 202-205 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76936 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76936 conf/iccad/1989 db/conf/iccad/iccad1989.html#NajmHY89 Daniel G. Saab Ibrahim N. Hajj Joseph T. Rahmeh Parallel-concurrent fault simulation. 298-301 1989 ICCD https://doi.org/10.1109/ICCD.1989.63376 conf/iccd/1989 db/conf/iccd/iccd1989.html#SaabHR89 Farid N. Najm Ibrahim N. Hajj Ping Yang 0001 Electromigration median time-to-failure based on a stochastic current waveform. 447-450 1989 ICCD https://doi.org/10.1109/ICCD.1989.63406 conf/iccd/1989 db/conf/iccd/iccd1989.html#NajmHY89 Daniel G. Saab Andrew T. Yang Ibrahim N. Hajj Delay Modeling and Time of Bipolar Digital Circuits. 288-293 1988 conf/dac/1988 DAC http://portal.acm.org/citation.cfm?id=285730.285777 db/conf/dac/dac88.html#SaabYH88 Tat-Kwan Yu Sung-Mo Kang Ibrahim N. Hajj Timothy N. Trick iEDISON: an interactive statistical design tool for MOS VLSI circuits. 20-23 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122454 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122454 conf/iccad/1988 db/conf/iccad/iccad1988.html#YuKHT88 David Overhauser Ibrahim N. Hajj A tabular macromodeling approach to fast timing simulation including parasitics. 70-73 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122465 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122465 conf/iccad/1988 db/conf/iccad/iccad1988.html#OverhauserH88 Farid N. Najm Richard Burch Ping Yang 0001 Ibrahim N. Hajj CREST-a current estimator for CMOS circuits. 204-207 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122494 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122494 conf/iccad/1988 db/conf/iccad/iccad1988.html#NajmBYH88 Mi-Chang Chang Ibrahim N. Hajj iPRIDE: a parallel integrated circuit simulator using direct method. 304-307 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122516 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122516 conf/iccad/1988 db/conf/iccad/iccad1988.html#ChangH88

Ibrahim N. Hajj Daniel G. Saab Switch-Level Logic Simulation of Digital Bipolar Circuits. 251-258 1987 6 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.1987.1270269 db/journals/tcad/tcad6.html#HajjS87

Ilan Algor Geng Bai Murat R. Becer Nikolaos Bellas David T. Blaauw Sudhakar Bobba Richard Burch Mi-Chang Chang Yu-Hsu Chang Tzuhao Chen Weitong Chuang Pi-Yu Chung W. Kent Fuchs P. Gee Shashank Goel Yi-Fan Hsu Young-Hyun Jun S. M. Kang Sung-Mo Kang Harish Kriplani Sangheon LeeSang-Heon Lee Terry Lee Rafi Levy Ping-Chung Li Ninglong Lu Makram M. Mansour Mohammad M. Mansour Farid N. Najm Chanhee Oh David Overhauser Rajendran Panda Song-Bai Park Janak H. Patel Constantine D. Polychronopoulos Joseph T. Rahmeh Sumant Ramprasad Elizabeth M. Rudnick Daniel G. Saab Sachin S. Sapatnekar Vikram Saxena Naresh R. Shanbhag Supamas Sirichotiyakul Stig Skelboe George D. Stamoulis Georgios I. StamoulisGeorge I. Stamoulis Timothy N. Trick Andreas G. Veneris Srikanth Venkataraman Yi-Min Wang Min-You Wu Andrew T. Yang Ping Yang 0001 Tat-Kwan Yu Vladimir Zolotov Jingyan Zuo