A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path.

Yifei Li Jian Chen Yuqi Wang 0004 Zihan Yin Hongyu Chen Yajun Ha A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. 1-2 2023 CICC https://doi.org/10.1109/CICC57935.2023.10121235 conf/cicc/2023 db/conf/cicc/cicc2023.html#LiCWYCH23