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ORCID15th HEART 2025: Kumamoto, Japan
- Tomohiro Ueno, Ameer Abdelhadi, Dirk Koch, Yasunori Osana, Yukinori Sato:
Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2025, Kumamoto, Japan, May 26-28, 2025. ACM 2025, ISBN 979-8-4007-1432-0 - Zhiqiang Que
, Hongxiang Fan, Gabriel F. Figueiredo, Ce Guo, Wayne Luk, Ryota Yasudo, Masato Motomura:
Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation. 1-13 - Mathias Bouilloud, Lana Josipovic, Wayne Luk:
Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis. 14-24 - Ce Guo, Tong Zhao:
ResBench: A Resource-Aware Benchmark for LLM-Generated FPGA Designs. 25-34 - Gerrit Pape, Bjarne Wintermann, Linus Jungemann, Michael Lass, Marius Meyer, Heinrich Riebler, Christian Plessl:
AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. 35-48 - Takumi Suzuki, Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku:
Accelerating Deep Learning Inference with a Parallel FPGA System. 49-56 - Kensuke Setsu, Ryota Miyagi, Hiroshi Nakamura, Hideki Takase:
Modeling Memory Usage in Training of Reversible Residual Network for Parallel Distributed Processing. 57-66 - Aditya Srichandan, Omar Ragheb, Jason Helge Anderson:
Systolic Array-Based Matrix Multiplication and Reduction on Elastic CGRAs. 67-75 - Yasuto Aihara, Boma Anantasatya Adhi, Kota Aiyoshi, Chenlin Shi, Jason Anderson, Tomohiro Ueno, Kentaro Sano, Takaaki Miyajima:
Impact of Reconvergent DFG Paths and Buffer Depth on Elastic CGRA Throughput. 76-79 - Geetesh More, Suprio Ray, Kenneth B. Kent:
Accelerating Learned Join with FPGAs in Relational Databases. 80-92 - Ludi Wang, Takeshi Ohkawa:
ROS 2-Integrated Low-Latency Remote Force Feedback System Using FPGA-Accelerated FOC Control and Inverse Kinematics. 93-102 - Linus Jungemann, Bjarne Wintermann, Heinrich Riebler, Christian Plessl:
FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC. 103-116 - Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano:
FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution. 117-125 - Prasoon Ambalathankandy, Werner Florian Samayoa, Jan-Erik R. Wichmann, Kentaro Sano:
Systolic array based syndrome graph pruning for quantum error correction using FPGAs. 126-130 - Kazuki Tokuishi, Motoki Amagasaki, Masato Kiyama, Kenshu Seto:
Enhancing FPGA Routing Efficiency with Graph Neural Network-Based Congestion Prediction. 131-137 - Kenshu Seto, Masahiro Iida:
Minimizing Local Interconnections to Reduce Chip Area in eFPGAs. 138-141 - Xiaoke Wang, Dirk Stroobandt:
Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs. 142-146 - Thalles M. Moreira, Fábio D. L. Coutinho, Arnaldo S. R. Oliveira:
AI Frameworks and DL Processing Units Performance Evaluation for CNN-Based Real-Time RF Modulation Classification. 147-155 - Marcus Bednara, Kristin Braun, Martina Kuchlbauer, Carsten Sigwarth:
Accelerating Linear Programming Performance: A Hardware-Software Co-Design Approach for the Simplex Method. 156-166 - Mika Bröker, Johannes Menzel, Christian Plessl:
Evaluating the Strong Scaling Potential of AI Engines for Molecular Dynamics Simulations. 167-171
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