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ORCID14th MTV 2013: Austin, TX, USA
- 14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-3246-7
- Brian Kahne, Jim Holt:
Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques. 3-7 - Mohamed A. Salem, Kerstin I. Eder
:
Modified Condition Decision Coverage: A Hardware Verification Perspective. 8-13 - Hoyoung Kim, Seonghun Jeong, Sunmin Kwon, Soojung Ryu:
Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System. 14-18 - Daniel Hansson, Heli Uronen-Hansson:
Measuring the Gain of Automatic Debug. 19-22 - Christian Miller, Christoph Scholl, Bernd Becker:
Proving QBF-hardness in Bounded Model Checking for Incomplete Designs. 23-28 - Abhishek Basak, Sanchita Mal-Sarkar, Swarup Bhunia:
Secure and Trusted SoC: Challenges and Emerging Solutions. 29-34 - Matthew L. King:
Practical Security Validation. 35-38 - Mona Safar, Magdy A. El-Moursy, Ashraf Salem:
Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation. 39-44 - Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia:
Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems. 45-51 - Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan:
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors. 52-57 - Narendra Kamat:
IP Testing for Heterogeneous SOCs. 58-61 - Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir:
Dynamic Selection of Trace Signals for Post-Silicon Debug. 62-67 - Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Francesco Stefanni:
Automatic Network Protocol Synthesis from UML Sequence Diagrams. 68-73 - Jack L. Mason, Gregory E. Simco:
Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution. 74-76 - Tariq Bashir Ahmad, Maciej J. Ciesielski:
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. 77-82 - Maneesh Kumar Pandey, Atul Gupta, Shwetank Shekhar:
USB Validation Challenges on C45SOI & C28NM Technology Products. 83-88 - Ujjwal Guin, Domenic Forte, Mohammad Tehranipoor:
Anti-counterfeit Techniques: From Design to Resign. 89-94 - Maneesh Kumar Pandey, Shwetank Shekhar, Nitin Saxena, Gaurav Kumar Agarwal, Amersh Kumar:
An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC. 95-99 - Vinayak Kamath, Farhan Rahman, Li-C. Wang:
Analyzing Efficacy of Constrained Test Program Generators - A Case Study. 100-105 - Rama Venkatasubramanian, Oluleye Olorode, Abhishek Arun:
State Retention Validation of C66X DSP Core. 106-111 - David Brier, Rama Venkatasubramanian, Sowmya Rangarajan, Abhishek Arun, David Thompson, Neelima Muralidharan:
Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip. 112-117
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