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Nannan Li
Publications
- 2026
[j40]Nannan Li, Lei Pei, Bin Liu, Hanrui Zhang, Jinfu Wang, Jie Zhang, Xiaofei Wang, Hong Zhang
:
A 14-bit 3 GS/s pipelined ADC featuring an input buffer with replica-based nonlinearity compensation in 28-nm CMOS technology. Microelectron. J. 168: 107015 (2026)- 2025
[j29]Nannan Li
, Hanrui Zhang
, Bin Liu
, Lei Pei, Jinfu Wang, Huanhuan Qi, Jie Zhang
, Xiaofei Wang
, Hong Zhang
:
A 10-Bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-Loop Amplifier and Parallel Conversion Through Comparator Reusing. IEEE Trans. Circuits Syst. II Express Briefs 72(2): 354-358 (2025)- 2023
[j14]Hanrui Zhang
, Nannan Li
, Jinfu Wang, Zihao Jiao
, Jie Zhang
, Xiaofei Wang
, Hong Zhang
:
A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3872-3876 (2023)- 2022
[j11]Hanrui Zhang
, Xiaofei Wang
, Nannan Li
, Zihao Jiao
, Liang Chen, Di Mu, Jie Zhang
, Hong Zhang
:
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer. IEEE Trans. Very Large Scale Integr. Syst. 30(12): 1928-1932 (2022)- 2021
[c9]Hanrui Zhang
, Nannan Li, Zihao Jiao, Jie Zhang, Xiaofei Wang, Hong Zhang:
A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration. ISCAS 2021: 1-5

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last updated on 2026-07-08 01:40 CEST by the dblp team
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