<?xml version="1.0"?>
<dblpperson name="Piao Zhe" pid="23/5825" n="4">
<person key="homepages/23/5825" mdate="2009-06-10">
<author pid="23/5825">Piao Zhe</author>
</person>
<r><article key="journals/ieicet/YasufukuNZTS11" mdate="2020-04-11">
<author pid="55/7550">Tadashi Yasufuku</author>
<author pid="99/7199">Yasumi Nakamura</author>
<author pid="23/5825">Piao Zhe</author>
<author pid="93/2018">Makoto Takamiya</author>
<author pid="37/6335">Takayasu Sakurai</author>
<title>Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.</title>
<pages>1072-1075</pages>
<year>2011</year>
<volume>94-C</volume>
<journal>IEICE Trans. Electron.</journal>
<number>6</number>
<ee>https://doi.org/10.1587/transele.E94.C.1072</ee>
<ee>http://search.ieice.org/bin/summary.php?id=e94-c_6_1072</ee>
<url>db/journals/ieicet/ieicet94c.html#YasufukuNZTS11</url>
</article>
</r>
<r><article key="journals/ieicet/YasufukuNZIMTS10" mdate="2020-04-11">
<author pid="55/7550">Tadashi Yasufuku</author>
<author pid="57/2791">Taro Niiyama</author>
<author pid="23/5825">Piao Zhe</author>
<author pid="00/4236">Koichi Ishida</author>
<author pid="21/1739">Masami Murakata</author>
<author pid="93/2018">Makoto Takamiya</author>
<author pid="37/6335">Takayasu Sakurai</author>
<title>Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.</title>
<pages>332-339</pages>
<year>2010</year>
<volume>93-C</volume>
<journal>IEICE Trans. Electron.</journal>
<number>3</number>
<ee>https://doi.org/10.1587/transele.E93.C.332</ee>
<ee>http://search.ieice.org/bin/summary.php?id=e93-c_3_332</ee>
<url>db/journals/ieicet/ieicet93c.html#YasufukuNZIMTS10</url>
</article>
</r>
<r><inproceedings key="conf/islped/NiiyamaPIMTS08" mdate="2025-01-19">
<author pid="57/2791">Taro Niiyama</author>
<author pid="23/5825">Piao Zhe</author>
<author pid="00/4236">Koichi Ishida</author>
<author pid="21/1739">Masami Murakata</author>
<author pid="93/2018">Makoto Takamiya</author>
<author pid="37/6335">Takayasu Sakurai</author>
<title>Increasing minimum operating voltage (V<sub>DDmin</sub>) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.</title>
<pages>117-122</pages>
<year>2008</year>
<booktitle>ISLPED</booktitle>
<ee>https://doi.org/10.1145/1393921.1393952</ee>
<ee>https://www.wikidata.org/entity/Q130887571</ee>
<crossref>conf/islped/2008</crossref>
<url>db/conf/islped/islped2008.html#NiiyamaPIMTS08</url>
</inproceedings>
</r>
<r><inproceedings key="conf/isqed/NiiyamaZIMTS08" mdate="2023-03-23">
<author pid="57/2791">Taro Niiyama</author>
<author pid="23/5825">Piao Zhe</author>
<author pid="00/4236">Koichi Ishida</author>
<author pid="21/1739">Masami Murakata</author>
<author pid="93/2018">Makoto Takamiya</author>
<author pid="37/6335">Takayasu Sakurai</author>
<title>Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.</title>
<pages>133-136</pages>
<year>2008</year>
<booktitle>ISQED</booktitle>
<ee>https://doi.org/10.1109/ISQED.2008.4479713</ee>
<ee>https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.59</ee>
<crossref>conf/isqed/2008</crossref>
<url>db/conf/isqed/isqed2008.html#NiiyamaZIMTS08</url>
</inproceedings>
</r>
<coauthors n="7" nc="1">
<co c="0"><na f="i/Ishida:Koichi" pid="00/4236">Koichi Ishida</na></co>
<co c="0"><na f="m/Murakata:Masami" pid="21/1739">Masami Murakata</na></co>
<co c="0"><na f="n/Nakamura:Yasumi" pid="99/7199">Yasumi Nakamura</na></co>
<co c="0"><na f="n/Niiyama:Taro" pid="57/2791">Taro Niiyama</na></co>
<co c="0"><na f="s/Sakurai:Takayasu" pid="37/6335">Takayasu Sakurai</na></co>
<co c="0"><na f="t/Takamiya:Makoto" pid="93/2018">Makoto Takamiya</na></co>
<co c="0"><na f="y/Yasufuku:Tadashi" pid="55/7550">Tadashi Yasufuku</na></co>
</coauthors>
</dblpperson>

