An accurate functional level concurrent fault simulator.

Edward W. Thompson Manuel A. d'Abreu Edward W. Thompson An accurate functional level concurrent fault simulator. 210-217 1980 DAC https://doi.org/10.1145/800139.804530 conf/dac/1980 db/conf/dac/dac1980.html#dAbreuT80 Edward W. Thompson Patrick G. Karger W. R. Read Jr. Don Ross John Smith Richard von Blucher The incorporation of functional level element routines into an existing digital simulation system. 394-401 1980 DAC https://doi.org/10.1145/800139.804561 conf/dac/1980 db/conf/dac/dac1980.html#ThompsonKRRSB80

Robert F. Bridge Edward W. Thompson Bridges: a tool for increasing the reliability of references to Fortran variables. 2-9 1976 11 ACM SIGPLAN Notices 9 https://doi.org/10.1145/987500.987502 https://www.wikidata.org/entity/Q130968926 db/journals/sigplan/sigplan11.html#BridgeT76

Stephen A. Szygenda Edward W. Thompson Modeling and Digital Simulation for Design Verification and Diagnosis. 1242-1253 1976 25 IEEE Trans. Computers 12 db/journals/tc/tc25.html#SzygendaT76 https://doi.org/10.1109/TC.1976.1674591 http://doi.ieeecomputersociety.org/10.1109/TC.1976.1674591

Stephen A. Szygenda Edward W. Thompson Digital Logic Simulation in a Time-Based, Table-Driven Environment. 24-36 1975 8 Computer 3 https://doi.org/10.1109/C-M.1975.218898 http://doi.ieeecomputersociety.org/10.1109/C-M.1975.218898 db/journals/computer/computer8.html#SzygendaT75

Edward W. Thompson Stephen A. Szygenda Digital Logic Simulation in a Time-Based, Table-Driven Environment. 38-49 1975 8 Computer 3 https://doi.org/10.1109/C-M.1975.218900 http://doi.ieeecomputersociety.org/10.1109/C-M.1975.218900 db/journals/computer/computer8.html#ThompsonS75

Edward W. Thompson Robert F. Bridge A module interface specification language. 42-49 1975 DAC http://dl.acm.org/citation.cfm?id=809049 conf/dac/1975 db/conf/dac/dac1975.html#ThompsonB75 Edward W. Thompson Stephen A. Szygenda Three levels of accuracy for the simulation of different fault types in digital systems. 105-113 1975 DAC http://dl.acm.org/citation.cfm?id=809057 conf/dac/1975 db/conf/dac/dac1975.html#ThompsonS75 Edward W. Thompson N. Billawala The software engineering technique of data hiding as applied to multi-level model implementation of logical devices in digital simulation. 195-201 1975 DAC http://dl.acm.org/citation.cfm?id=809067 conf/dac/1975 db/conf/dac/dac1975.html#ThompsonB75a Edward W. Thompson Stephen A. Szygenda N. Billawala R. Pierce Timing analysis for digital fault simulation using assignable delays. 266-272 1974 DAC http://dl.acm.org/citation.cfm?id=811402 conf/dac/1974 db/conf/dac/dac1974.html#ThompsonSBP74 Stephen A. Szygenda Edward W. Thompson Fault insertion techniques and models for digital logic simulation. 875-884 1972 conf/afips/1972f2 AFIPS Fall Joint Computing Conference (2) https://doi.org/10.1145/1480083.1480112 db/conf/afips/afips72f2.html#SzygendaT72 Stephen A. Szygenda David M. Rouse Edward W. Thompson A model and implementation of a universal time delay simulator for large digital nets. 207-216 1970 AFIPS Spring Joint Computing Conference https://doi.org/10.1145/1476936.1476973 conf/afips/1970s db/conf/afips/afips70s.html#SzygendaRT70 N. Billawala Richard von Blucher Robert F. Bridge Manuel A. d'Abreu Patrick G. Karger R. Pierce W. R. Read Jr. Don Ross David M. Rouse John Smith Stephen A. Szygenda