Pekka Neittaanmäki

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Svetlana M. Seledzhi

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Publications

2013
[c14]
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Nikolay V. Kuznetsov, Gennady A. Leonov, Pekka Neittaanmäki, Svetlana M. Seledzhi, Marat V. Yuldashev, Renat V. Yuldashev:
Phase-frequency Domain Model of Costas Loop with Mixer Discriminator. ICINCO (1) 2013: 427-433
2012
[c11]
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Nikolay V. Kuznetsov, Gennady A. Leonov, Pekka Neittaanmäki, Svetlana M. Seledzhi, Marat V. Yuldashev, Renat V. Yuldashev:
Simulation of phase-locked loops in phase-frequency domain. ICUMT 2012: 351-356
2011
[c8]
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Nikolay V. Kuznetsov, Gennady A. Leonov, Pekka Neittaanmäki, Svetlana M. Seledzhi, Marat V. Yuldashev, Renat V. Yuldashev:
High-frequency Analysis of Phase-locked Loop and Phase Detector Characteristic Computation. ICINCO (1) 2011: 272-278
2010
[c7]
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Gennady A. Leonov, Svetlana M. Seledzhi, Nikolay V. Kuznetsov, Pekka Neittaanmäki:
Asymptotic Analysis of Phase Control System for Clocks in Multiprocessor Arrays. ICINCO (3) 2010: 99-102
[c6]
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Nikolay V. Kuznetsov, Gennady A. Leonov, Pekka Neittaanmäki, Svetlana M. Seledzhi, Marat V. Yuldashev, Renat V. Yuldashev:
Nonlinear analysis of phase-locked loop. PSYCO 2010: 34-38
2009
[c4]
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Nikolay V. Kuznetsov, Gennady A. Leonov, Svetlana M. Seledzhi, Pekka Neittaanmäki:
Analysis and Design of Computer Architecture Circuits with Controllable Delay Line. ICINCO-SPSMC 2009: 221-224

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