A Scalable and Energy-Efficient Processing-in-Memory Architecture for Gen-AI.

Sarma B. K. Vrudhula Sarma Vrudhula https://orcid.org/0000-0001-9278-2959 https://www.wikidata.org/entity/Q130950575

Gian Singh Sarma Vrudhula A Scalable and Energy-Efficient Processing-in-Memory Architecture for Gen-AI. 285-298 2025 June 15 IEEE J. Emerg. Sel. Topics Circuits Syst. 2 https://doi.org/10.1109/JETCAS.2025.3566929 db/journals/esticas/esticas15.html#SinghV25 streams/journals/esticas

Mehdi Ghasemi 0003 Soroush Heidari Young Geun Kim 0001 Carole-Jean Wu Sarma B. K. Vrudhula Energy-Efficient, Delay-Constrained Edge Computing of a Network of DNNs. 569-581 2025 February 74 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2024.3500368 db/journals/tc/tc74.html#GhasemiHKWV25 streams/journals/tc

Soroush Heidari Mehdi Ghasemi 0003 Sarma Vrudhula Uncertainty-Aware RL-Based Scheduling of Multi-DNN Workloads on Edge MPSoCs. 11:1-11:16 2025 SEC https://doi.org/10.1145/3769102.3770621 conf/ieeesec/2025 db/conf/ieeesec/sec2025.html#Heidari0V25 Ayushi Dube Gian Singh Sarma Vrudhula A Compact, Low Power Transprecision ALU for Smart Edge Devices. 1-8 2025 ISLPED https://doi.org/10.1109/ISLPED65674.2025.11261699 conf/islped/2025 db/conf/islped/islped2025.html#DubeSV25 streams/conf/islped

Ayushi Dube Gian Singh Sarma Vrudhula A Compact, Low Power Transprecision ALU for Smart Edge Devices. 2025 October abs/2510.00333 CoRR https://doi.org/10.48550/arXiv.2510.00333 db/journals/corr/corr2510.html#abs-2510-00333 streams/journals/corr

Ankit Wagle Gian Singh Sunil P. Khatri Sarma B. K. Vrudhula An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. 2057-2070 2024 July 43 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2024.3357597 db/journals/tcad/tcad43.html#WagleSKV24

Kyler R. Scott Cheng-Yen Lee Sunil P. Khatri Sarma B. K. Vrudhula A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. 1025-1038 2024 March 71 IEEE Trans. Circuits Syst. I Regul. Pap. 3 https://doi.org/10.1109/TCSI.2023.3336248 db/journals/tcasI/tcasI71.html#ScottLKV24

Gian Singh Sarma B. K. Vrudhula A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. 57-62 2024 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3649476.3658732 https://www.wikidata.org/entity/Q130950576 conf/glvlsi/2024 db/conf/glvlsi/glvlsi2024.html#SinghV24 Chetan Choppali Sudarshan Nikhil Matkar Sarma B. K. Vrudhula Sachin S. Sapatnekar Vidya A. Chhabria ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. 671-685 2024 HPCA https://doi.org/10.1109/HPCA57654.2024.00058 conf/hpca/2024 db/conf/hpca/hpca2024.html#SudarshanMVSC24 Soroush Heidari Mehdi Ghasemi 0003 Young Geun Kim 0001 Carole-Jean Wu Sarma B. K. Vrudhula Elastic Execution of Multi-Tenant DNNs on Heterogeneous Edge MPSoCs. 279-291 2024 SEC https://doi.org/10.1109/SEC62691.2024.00029 conf/ieeesec/2024 db/conf/ieeesec/sec2024.html#Heidari0KWV24 Ayushi Dube Omkar Patil Gian Singh Nakul Gopalan Sarma B. K. Vrudhula Hardware-Software Co-Design for Path Planning by Drones. 8141-8146 2024 IROS https://doi.org/10.1109/IROS58592.2024.10802753 conf/iros/2024 db/conf/iros/iros2024.html#DubePSGV24 Gian Singh Ayushi Dube Sarma B. K. Vrudhula Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture. 186-191 2024 ISVLSI https://doi.org/10.1109/ISVLSI61997.2024.00043 conf/isvlsi/2024 db/conf/isvlsi/isvlsi2024.html#SinghDV24 streams/conf/isvlsi Gyudong Kim Mehdi Ghasemi 0003 Soroush Heidari Seungryong Kim Young Geun Kim 0001 Sarma B. K. Vrudhula Carole-Jean Wu HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. 2024 MLSys https://proceedings.mlsys.org/paper_files/paper/2024/hash/0badcb4e95306df76a719409155e46e8-Abstract-Conference.html conf/mlsys/2024 db/conf/mlsys/mlsys2024.html#Kim0HKKVW24 Gian Singh Ayushi Dube Sarma B. K. Vrudhula A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. 1-6 2024 VLSI-SoC https://doi.org/10.1109/VLSI-SoC62099.2024.10767834 conf/vlsi/2024 db/conf/vlsi/vlsisoc2024.html#SinghDV24

Gyudong Kim Mehdi Ghasemi 0003 Soroush Heidari Seungryong Kim Young Geun Kim 0001 Sarma B. K. Vrudhula Carole-Jean Wu HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. 2024 abs/2403.04207 CoRR https://doi.org/10.48550/arXiv.2403.04207 db/journals/corr/corr2403.html#abs-2403-04207

Ankit Wagle Jinghua Yang Niranjan Kulkarni Sarma B. K. Vrudhula A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. 4164-4176 2023 November 42 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2023.3264798 db/journals/tcad/tcad42.html#WagleYKV23

Gian Singh Sanmukh R. Kuppannagari Sarma B. K. Vrudhula PARAG: PIM Architecture for Real-Time Acceleration of GCNs. 11-20 2023 HiPC https://doi.org/10.1109/HiPC58850.2023.00016 conf/hipc/2023 db/conf/hipc/hipc2023.html#SinghKV23 Cheng-Yen Lee Sunil P. Khatri Sarma B. K. Vrudhula A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. 1-7 2023 ISQED https://doi.org/10.1109/ISQED57927.2023.10129385 conf/isqed/2023 db/conf/isqed/isqed2023.html#LeeKV23

Vidya A. Chhabria Chetan Choppali Sudarshan Sarma B. K. Vrudhula Sachin S. Sapatnekar Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. 2023 abs/2306.09434 CoRR https://doi.org/10.48550/arXiv.2306.09434 db/journals/corr/corr2306.html#abs-2306-09434

Soroush Heidari Mehdi Ghasemi 0003 Young Geun Kim 0001 Carole-Jean Wu Sarma B. K. Vrudhula CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs. 3191-3202 2022 71 IEEE Trans. Computers 12 https://doi.org/10.1109/TC.2022.3207137 db/journals/tc/tc71.html#HeidariGKWV22

Ankit Wagle Sarma B. K. Vrudhula Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. 1855-1867 2022 41 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/TCAD.2021.3099780 https://www.wikidata.org/entity/Q114147807 db/journals/tcad/tcad41.html#WagleV22

Ankit Wagle Gian Singh Sunil P. Khatri Sarma B. K. Vrudhula A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. 2968-2981 2022 69 IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2022.3164995 db/journals/tcasI/tcasI69.html#WagleSKV22

Mehdi Ghasemi 0003 Daler N. Rakhmatov Carole-Jean Wu Sarma B. K. Vrudhula EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays. 66:1-66:27 2022 September 21 ACM Trans. Embed. Comput. Syst. 5 https://doi.org/10.1145/3530908 https://www.wikidata.org/entity/Q130956625 db/journals/tecs/tecs21.html#GhasemiRWV22

Kyler R. Scott Cheng-Yen Lee Sunil P. Khatri Sarma B. K. Vrudhula A Flash-based Current-mode IC to Realize Quantized Neural Networks. 1029-1034 2022 DATE https://doi.org/10.23919/DATE54114.2022.9774539 conf/date/2022 db/conf/date/date2022.html#ScottLKV22 Ayushi Dube Ankit Wagle Gian Singh Sarma B. K. Vrudhula Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. 151:1-151:9 2022 ICCAD https://doi.org/10.1145/3508352.3549385 https://ieeexplore.ieee.org/document/10068917 https://www.wikidata.org/entity/Q130827572 conf/iccad/2022 db/conf/iccad/iccad2022.html#DubeWSV22

Ankit Wagle Gian Singh Sunil P. Khatri Sarma B. K. Vrudhula A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. 2022 abs/2204.08070 CoRR https://doi.org/10.48550/arXiv.2204.08070 db/journals/corr/corr2204.html#abs-2204-08070

Gian Singh Ankit Wagle Sarma B. K. Vrudhula Sunil P. Khatri CIDAN: Computing in DRAM with Artificial Neurons. 349-356 2021 ICCD https://doi.org/10.1109/ICCD53106.2021.00062 conf/iccd/2021 db/conf/iccd/iccd2021.html#SinghWVK21 Mehdi Ghasemi 0003 Soroush Heidari Young Geun Kim 0001 Aaron Lamb Carole-Jean Wu Sarma B. K. Vrudhula Energy-Efficient Mapping for a Network of DNN Models at the Edge. 25-30 2021 SMARTCOMP https://doi.org/10.1109/SMARTCOMP52413.2021.00024 conf/smartcomp/2021 db/conf/smartcomp/smartcomp2021.html#GhasemiHKLWV21

Ankit Wagle Sunil P. Khatri Sarma B. K. Vrudhula A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. 2021 abs/2104.01699 CoRR https://arxiv.org/abs/2104.01699 db/journals/corr/corr2104.html#abs-2104-01699

Gian Singh Ankit Wagle Sarma B. K. Vrudhula Sunil P. Khatri CIDAN: Computing in DRAM with Artificial Neurons. 2021 abs/2112.00117 CoRR https://arxiv.org/abs/2112.00117 db/journals/corr/corr2112.html#abs-2112-00117

Yufei Ma 0002 Yu Cao 0001 Sarma B. K. Vrudhula Jae-Sun Seo Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. 424-437 2020 39 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2018.2884972 https://www.wikidata.org/entity/Q128826932 db/journals/tcad/tcad39.html#MaCVS20

Yufei Ma 0002 Yu Cao 0001 Sarma B. K. Vrudhula Jae-Sun Seo Performance Modeling for CNN Inference Accelerators on FPGA. 843-856 2020 39 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2019.2897634 https://www.wikidata.org/entity/Q128492812 db/journals/tcad/tcad39.html#MaCVS20a

Elham Azari Sarma B. K. Vrudhula ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. 3:1-3:21 2020 19 ACM Trans. Embed. Comput. Syst. 1 https://doi.org/10.1145/3366634 db/journals/tecs/tecs19.html#AzariV20

Mohammad Farhadi Mehdi Ghasemi 0003 Sarma B. K. Vrudhula Yezhou Yang Enabling Incremental Knowledge Transfer for Object Detection at the Edge. 1591-1599 2020 CVPR Workshops https://openaccess.thecvf.com/content_CVPRW_2020/html/w28/Farhadi_Enabling_Incremental_Knowledge_Transfer_for_Object_Detection_at_the_Edge_CVPRW_2020_paper.html https://doi.org/10.1109/CVPRW50498.2020.00206 conf/cvpr/2020w db/conf/cvpr/cvprw2020.html#FarhadiGVY20 Ankit Wagle Sunil P. Khatri Sarma B. K. Vrudhula A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. 433-440 2020 ICCD https://doi.org/10.1109/ICCD50377.2020.00079 conf/iccd/2020 db/conf/iccd/iccd2020.html#WagleKV20 Elham Azari Ankit Wagle Sunil P. Khatri Sarma B. K. Vrudhula A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. 141-148 2020 ISQED https://doi.org/10.1109/ISQED48828.2020.9136979 conf/isqed/2020 db/conf/isqed/isqed2020.html#AzariWKV20

Mohammad Farhadi Bajestani Mehdi Ghasemi 0003 Sarma B. K. Vrudhula Yezhou Yang Enabling Incremental Knowledge Transfer for Object Detection at the Edge. 2020 abs/2004.05746 CoRR https://arxiv.org/abs/2004.05746 db/journals/corr/corr2004.html#abs-2004-05746

Benjamin Gaudette Carole-Jean Wu Sarma B. K. Vrudhula Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties. 2941-2953 2019 18 IEEE Trans. Mob. Comput. 12 https://doi.org/10.1109/TMC.2018.2883619 https://www.wikidata.org/entity/Q128859660 db/journals/tmc/tmc18.html#GaudetteWV19

Elham Azari Sarma B. K. Vrudhula An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing. 4450-4459 2019 IEEE BigData https://doi.org/10.1109/BigData47090.2019.9006030 conf/bigdataconf/2019 db/conf/bigdataconf/bigdataconf2019.html#AzariV19 Elham Azari Aykut Dengi Sarma B. K. Vrudhula An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. 305-306 2019 FPGA https://doi.org/10.1145/3289602.3293989 https://www.wikidata.org/entity/Q130840182 conf/fpga/2019 db/conf/fpga/fpga2019.html#AzariDV19 Ankit Wagle Elham Azari Sarma B. K. Vrudhula Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. 1-8 2019 ICCAD https://doi.org/10.1109/ICCAD45719.2019.8942071 conf/iccad/2019 db/conf/iccad/iccad2019.html#WagleAV19 Ankit Wagle Gian Singh Jinghua Yang Sunil P. Khatri Sarma B. K. Vrudhula Threshold Logic in a Flash. 550-558 2019 ICCD https://doi.org/10.1109/ICCD46524.2019.00081 conf/iccd/2019 db/conf/iccd/iccd2019.html#WagleSYKV19

Ankit Wagle Gian Singh Jinghua Yang Sunil P. Khatri Sarma B. K. Vrudhula Threshold Logic in a Flash. 2019 abs/1910.04910 CoRR http://arxiv.org/abs/1910.04910 db/journals/corr/corr1910.html#abs-1910-04910

Elham Azari Sarma B. K. Vrudhula ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. 2019 abs/1910.08683 CoRR http://arxiv.org/abs/1910.08683 db/journals/corr/corr1910.html#abs-1910-08683

Yufei Ma 0002 Naveen Suda Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. 14-23 2018 62 Integr. https://doi.org/10.1016/j.vlsi.2017.12.009 https://www.wikidata.org/entity/Q123020098 db/journals/integration/integration62.html#MaSCVS18

Yufei Ma 0002 Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. 1354-1367 2018 26 IEEE Trans. Very Large Scale Integr. Syst. 7 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2815603 db/journals/tvlsi/tvlsi26.html#MaCVS18

Jinghua Yang Aykut Dengi Sarma B. K. Vrudhula Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. 2628-2640 2018 26 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2018.2812700 db/journals/tvlsi/tvlsi26.html#YangDV18

Ankit Wagle Jinghua Yang Aykut Dengi Sarma B. K. Vrudhula FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. 256-259 2018 FPL https://doi.org/10.1109/FPL.2018.00051 https://doi.ieeecomputersociety.org/10.1109/FPL.2018.00051 conf/fpl/2018 db/conf/fpl/fpl2018.html#WagleYDV18 Yufei Ma 0002 Tu Zheng Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. 57 2018 ICCAD https://doi.org/10.1145/3240765.3240775 https://ieeexplore.ieee.org/document/8587767/ conf/iccad/2018 db/conf/iccad/iccad2018.html#MaZ0VS18 Davesh Shingari Akhil Arunkumar Benjamin Gaudette Sarma B. K. Vrudhula Carole-Jean Wu DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference. 64-75 2018 ISPASS https://doi.org/10.1109/ISPASS.2018.00015 https://doi.ieeecomputersociety.org/10.1109/ISPASS.2018.00015 conf/ispass/2018 db/conf/ispass/ispass2018.html#ShingariAGVW18 Niranjan Kulkarni Aykut Dengi Sarma B. K. Vrudhula A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. 67:1-67:6 2017 DAC https://doi.org/10.1145/3061639.3062183 conf/dac/2017 db/conf/dac/dac2017.html#KulkarniDV17 Yufei Ma 0002 Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. 45-54 2017 FPGA http://dl.acm.org/citation.cfm?id=3021736 conf/fpga/2017 db/conf/fpga/fpga2017.html#MaCVS17 Yufei Ma 0002 Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. 1-8 2017 FPL https://doi.org/10.23919/FPL.2017.8056824 conf/fpl/2017 db/conf/fpl/fpl2017.html#MaCVS17 Yufei Ma 0002 Minkyu Kim 0001 Yu Cao 0001 Sarma B. K. Vrudhula Jae-sun Seo End-to-end scalable FPGA accelerator for deep residual networks. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050344 conf/iscas/2017 db/conf/iscas/iscas2017.html#MaKCVS17 Mehmet Ince Sule Ozev Sarma B. K. Vrudhula Statistical library characterization using arbitrary polynomial chaos. 1-4 2017 LASCAS https://doi.org/10.1109/LASCAS.2017.7948078 conf/lascas/2017 db/conf/lascas/lascas2017.html#InceOV17

Niranjan Kulkarni Jinghua Yang Jae-sun Seo Sarma B. K. Vrudhula Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. 2873-2886 2016 24 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2016.2527783 db/journals/tvlsi/tvlsi24.html#KulkarniYSV16

Naveen Suda Vikas Chandra Ganesh Dasika Abinash Mohanty Yufei Ma 0002 Sarma B. K. Vrudhula Jae-sun Seo Yu Cao 0001 Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. 16-25 2016 FPGA https://doi.org/10.1145/2847263.2847276 https://www.wikidata.org/entity/Q130846789 conf/fpga/2016 db/conf/fpga/fpga2016.html#SudaCDMMVSC16 Yufei Ma 0002 Naveen Suda Yu Cao 0001 Jae-sun Seo Sarma B. K. Vrudhula Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. 1-8 2016 FPL https://doi.org/10.1109/FPL.2016.7577356 conf/fpl/2016 db/conf/fpl/fpl2016.html#MaSCSV16 Benjamin Gaudette Carole-Jean Wu Sarma B. K. Vrudhula Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee. 52-63 2016 HPCA https://doi.org/10.1109/HPCA.2016.7446053 https://doi.ieeecomputersociety.org/10.1109/HPCA.2016.7446053 conf/hpca/2016 db/conf/hpca/hpca2016.html#GaudetteWV16 Abinash Mohanty Naveen Suda Minkyu Kim 0001 Sarma B. K. Vrudhula Jae-sun Seo Yu Cao 0001 High-performance face detection with CPU-FPGA acceleration. 117-120 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7527184 conf/iscas/2016 db/conf/iscas/iscas2016.html#MohantySKVSC16 Debayan Mahalanabis M. Sivaraj W. Chen S. Shah Hugh J. Barnaby Michael N. Kozicki Jennifer Blain Christen Sarma B. K. Vrudhula Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons. 2314-2317 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7539047 conf/iscas/2016 db/conf/iscas/iscas2016.html#MahalanabisSCSB16 Joseph Davis Niranjan Kulkarni Jinghua Yang Aykut Dengi Sarma B. K. Vrudhula Digital IP protection using threshold voltage control. 344-349 2016 ISQED https://doi.org/10.1109/ISQED.2016.7479225 conf/isqed/2016 db/conf/isqed/isqed2016.html#DavisKYDV16

Joseph Davis Niranjan Kulkarni Jinghua Yang Aykut Dengi Sarma B. K. Vrudhula Digital IP Protection Using Threshold Voltage Control. 2016 abs/1603.07370 CoRR http://arxiv.org/abs/1603.07370 db/journals/corr/corr1603.html#DavisKYDV16

Niranjan Kulkarni Sarma B. K. Vrudhula Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. 2016 abs/1603.07371 CoRR http://arxiv.org/abs/1603.07371 db/journals/corr/corr1603.html#KulkarniV16

Deepak Kadetotad Zihan Xu Abinash Mohanty Pai-Yu Chen Binbin Lin Jieping Ye Sarma B. K. Vrudhula Shimeng Yu Yu Cao 0001 Jae-sun Seo Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. 194-204 2015 5 IEEE J. Emerg. Sel. Topics Circuits Syst. 2 https://doi.org/10.1109/JETCAS.2015.2426495 db/journals/esticas/esticas5.html#KadetotadXMCLYV15

Debayan Mahalanabis Vineeth Bharadwaj Hugh J. Barnaby Sarma B. K. Vrudhula Michael N. Kozicki A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells. 205-213 2015 5 IEEE J. Emerg. Sel. Topics Circuits Syst. 2 https://doi.org/10.1109/JETCAS.2015.2433571 db/journals/esticas/esticas5.html#MahalanabisBBVK15

Andreas Thor Winther Wei Liu 0016 Alberto Nannarelli Sarma B. K. Vrudhula Thermal aware floorplanning incorporating temperature dependent wire delay estimation. 807-815 2015 39 Microprocess. Microsystems 8 https://doi.org/10.1016/j.micpro.2015.09.013 db/journals/mam/mam39.html#WintherLNV15

Jinghua Yang Joseph Davis Niranjan Kulkarni Jae-sun Seo Sarma B. K. Vrudhula Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. 1-4 2015 CICC https://doi.org/10.1109/CICC.2015.7338369 conf/cicc/2015 db/conf/cicc/cicc2015.html#YangDKSV15 Pai-Yu Chen Deepak Kadetotad Zihan Xu Abinash Mohanty Binbin Lin Jieping Ye Sarma B. K. Vrudhula Jae-sun Seo Yu Cao 0001 Shimeng Yu Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. 854-859 2015 DATE http://dl.acm.org/citation.cfm?id=2755947 https://ieeexplore.ieee.org/document/7092504/ conf/date/2015 db/conf/date/date2015.html#ChenKXMLYVSCY15 Pai-Yu Chen Binbin Lin I-Ting Wang Tuo-Hung Hou Jieping Ye Sarma B. K. Vrudhula Jae-sun Seo Yu Cao 0001 Shimeng Yu Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. 194-199 2015 ICCAD https://doi.org/10.1109/ICCAD.2015.7372570 http://dl.acm.org/citation.cfm?id=2840848 conf/iccad/2015 db/conf/iccad/iccad2015.html#ChenLWHYVSCY15 Yufei Ma 0002 Minkyu Kim 0001 Yu Cao 0001 Jae-sun Seo Sarma B. K. Vrudhula Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. 443-446 2015 ICCD https://doi.org/10.1109/ICCD.2015.7357144 https://doi.ieeecomputersociety.org/10.1109/ICCD.2015.7357144 conf/iccd/2015 db/conf/iccd/iccd2015.html#MaKCSV15 Sarma B. K. Vrudhula Niranjan Kulkarni Jinghua Yang Design of threshold logic gates using emerging devices. 373-376 2015 ISCAS https://doi.org/10.1109/ISCAS.2015.7168648 conf/iscas/2015 db/conf/iscas/iscas2015.html#VrudhulaKY15 Jinghua Yang Niranjan Kulkarni Joseph Davis Sarma B. K. Vrudhula Fast and robust differential flipflops and their extension to multi-input threshold gates. 822-825 2015 ISCAS https://doi.org/10.1109/ISCAS.2015.7168760 conf/iscas/2015 db/conf/iscas/iscas2015.html#YangKDV15

Zihan Xu Matteo Cavaliere Pei An Sarma B. K. Vrudhula Yu Cao 0001 The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. 183-200 2014 134 Fundam. Informaticae 1-2 https://doi.org/10.3233/FI-2014-1098 db/journals/fuin/fuin134.html#XuCAVC14

Nishant Nukala Niranjan Kulkarni Sarma B. K. Vrudhula Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. 2452-2460 2014 74 J. Parallel Distributed Comput. 6 https://doi.org/10.1016/j.jpdc.2013.09.013 db/journals/jpdc/jpdc74.html#NukalaKV14

Vinay Hanumaiah Sarma B. K. Vrudhula Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling. 349-360 2014 63 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2012.213 http://doi.ieeecomputersociety.org/10.1109/TC.2012.213 db/journals/tc/tc63.html#HanumaiahV14

Vinay Hanumaiah Digant Desai Benjamin Gaudette Carole-Jean Wu Sarma B. K. Vrudhula STEAM: A Smart Temperature and Energy Aware Multicore Controller. 151:1-151:25 2014 13 ACM Trans. Embed. Comput. Syst. 5s https://doi.org/10.1145/2661430 db/journals/tecs/tecs13.html#HanumaiahDGWV14

Benjamin Gaudette Vinay Hanumaiah Marwan Krunz Sarma B. K. Vrudhula Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks. 59:1-59:27 2014 10 ACM Trans. Sens. Networks 4 https://doi.org/10.1145/2594792 db/journals/tosn/tosn10.html#GaudetteHKV14

Zihan Xu Abinash Mohanty Pai-Yu Chen Deepak Kadetotad Binbin Lin Jieping Ye Sarma B. K. Vrudhula Shimeng Yu Jae-sun Seo Yu Cao 0001 Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. 126-133 2014 BICA https://doi.org/10.1016/j.procs.2014.11.094 conf/bica/2014 db/conf/bica/bica2014.html#XuMCKLYVYSC14 Deepak Kadetotad Zihan Xu Abinash Mohanty Pai-Yu Chen Binbin Lin Jieping Ye Sarma B. K. Vrudhula Shimeng Yu Yu Cao 0001 Jae-sun Seo Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. 536-539 2014 BioCAS https://doi.org/10.1109/BioCAS.2014.6981781 conf/biocas/2014 db/conf/biocas/biocas2014.html#KadetotadXMCLYV14 Mahdi Hamzeh Aviral Shrivastava Sarma B. K. Vrudhula Branch-Aware Loop Mapping on CGRAs. 107:1-107:6 2014 DAC https://doi.org/10.1145/2593069.2593100 conf/dac/2014 db/conf/dac/dac2014.html#HamzehSV14 Niranjan Kulkarni Jinghua Yang Sarma B. K. Vrudhula A fast, energy efficient, field programmable threshold-logic array. 300-305 2014 FPT https://doi.org/10.1109/FPT.2014.7082804 conf/fpt/2014 db/conf/fpt/fpt2014.html#KulkarniYV14 Jinghua Yang Niranjan Kulkarni Shimeng Yu Sarma B. K. Vrudhula Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. 39-44 2014 NANOARCH https://doi.org/10.1109/NANOARCH.2014.6880500 https://doi.ieeecomputersociety.org/10.1109/NANOARCH.2014.6880500 https://doi.org/10.1145/2770287.2770298 https://www.wikidata.org/entity/Q130888024 conf/nanoarch/2014 db/conf/nanoarch/nanoarch2014.html#YangKYV14 Mahdi Hamzeh Aviral Shrivastava Sarma B. K. Vrudhula REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). 18:1-18:10 2013 DAC https://doi.org/10.1145/2463209.2488756 conf/dac/2013 db/conf/dac/dac2013.html#HamzehSV13

Vinay Hanumaiah Sarma B. K. Vrudhula Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors. 1484-1494 2012 61 IEEE Trans. Computers 10 https://doi.org/10.1109/TC.2011.156 http://doi.ieeecomputersociety.org/10.1109/TC.2011.156 db/journals/tc/tc61.html#HanumaiahV12

Mahdi Hamzeh Aviral Shrivastava Sarma B. K. Vrudhula EPIMap: using epimorphism to map applications on CGRAs. 1284-1291 2012 DAC https://doi.org/10.1145/2228360.2228600 conf/dac/2012 db/conf/dac/dac2012.html#HamzehSV12 Niranjan Kulkarni Nishant Nukala Sarma B. K. Vrudhula Minimizing area and power of sequential CMOS circuits using threshold decomposition. 605-612 2012 ICCAD https://doi.org/10.1145/2429384.2429514 https://ieeexplore.ieee.org/document/6386734/ conf/iccad/2012 db/conf/iccad/iccad2012.html#KulkarniNV12 Benjamin Gaudette Vinay Hanumaiah Sarma B. K. Vrudhula Marwan Krunz Optimal range assignment in solar powered active wireless sensor networks. 2354-2362 2012 INFOCOM https://doi.org/10.1109/INFCOM.2012.6195623 conf/infocom/2012 db/conf/infocom/infocom2012.html#GaudetteHVK12 Nishant Nukala Niranjan Kulkarni Sarma B. K. Vrudhula Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. 188-195 2012 NANOARCH https://doi.org/10.1145/2765491.2765525 https://ieeexplore.ieee.org/document/6464162/ conf/nanoarch/2012 db/conf/nanoarch/nanoarch2012.html#NukalaKV12

Tejaswi Gowda Sarma B. K. Vrudhula Niranjan Kulkarni Krzysztof S. Berezowski Identification of Threshold Functions and Synthesis of Threshold Networks. 665-677 2011 30 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2010.2100232 db/journals/tcad/tcad30.html#GowdaVKB11

Vinay Hanumaiah Sarma B. K. Vrudhula Karam S. Chatha Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. 1677-1690 2011 30 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2011.2161308 db/journals/tcad/tcad30.html#HanumaiahVC11

Vinay Hanumaiah Sarma B. K. Vrudhula Reliability-aware thermal management for hard real-time applications on multi-core processors. 137-142 2011 DATE https://doi.org/10.1109/DATE.2011.5763032 https://doi.ieeecomputersociety.org/10.1109/DATE.2011.5763032 conf/date/2011 db/conf/date/date2011.html#HanumaiahV11 Gayathri Chalivendra Vinay Hanumaiah Sarma B. K. Vrudhula A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation. 139-144 2011 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1973009.1973038 conf/glvlsi/2011 db/conf/glvlsi/glvlsi2011.html#ChalivendraHV11 Aviral Shrivastava Jared Pager Reiley Jeyapaul Mahdi Hamzeh Sarma B. K. Vrudhula Enabling Multithreading on CGRAs. 255-264 2011 ICPP https://doi.org/10.1109/ICPP.2011.77 https://doi.ieeecomputersociety.org/10.1109/ICPP.2011.77 conf/icpp/2011 db/conf/icpp/icpp2011.html#ShrivastavaPJHV11 Andreas Thor Winther Wei Liu 0016 Alberto Nannarelli Sarma B. K. Vrudhula Temperature dependent wire delay estimation in floorplanning. 1-4 2011 NORCHIP https://doi.org/10.1109/NORCHP.2011.6126741 conf/norchip/2011 db/conf/norchip/norchip2011.html#WintherLNV11

Wenping Wang 0004 Shengqi Yang Sarvesh Bhardwaj Sarma B. K. Vrudhula Frank Liu 0001 Yu Cao 0001 The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. 173-183 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/TVLSI.2008.2008810 db/journals/tvlsi/tvlsi18.html#WangYBVLC10

Aviral Shrivastava Deepa Kannan Sarvesh Bhardwaj Sarma B. K. Vrudhula Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. 988-997 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2009.2019082 db/journals/tvlsi/tvlsi18.html#ShrivastavaKBV10

Samuel Leshner Krzysztof S. Berezowski Xiaoyin Yao Gayathri Chalivendra Saurabh Patel Sarma B. K. Vrudhula A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. 210-215 2010 ISVLSI https://doi.org/10.1109/ISVLSI.2010.32 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2010.32 conf/isvlsi/2010 db/conf/isvlsi/isvlsi2010.html#LeshnerBYCPV10

Ravishankar Rao Sarma B. K. Vrudhula Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. 1559-1572 2009 28 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2009.2026361 db/journals/tcad/tcad28.html#RaoV09

Jianli Zhuo Chaitali Chakrabarti Kyungsoo Lee Naehyuck Chang Sarma B. K. Vrudhula Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. 22-32 2009 17 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2008.2008432 db/journals/tvlsi/tvlsi17.html#ZhuoCLCV09

Michael A. Baker Pravin Dalale Karam S. Chatha Sarma B. K. Vrudhula A scalable parallel H.264 decoder on the cell broadband engine architecture. 353-362 2009 CODES+ISSS https://doi.org/10.1145/1629435.1629484 conf/codes/2009 db/conf/codes/codes2009.html#BakerDCV09 Vinay Hanumaiah Ravishankar Rao Sarma B. K. Vrudhula Karam S. Chatha Throughput optimal task allocation under thermal constraints for multi-core processors. 776-781 2009 DAC https://doi.org/10.1145/1629911.1630112 conf/dac/2009 db/conf/dac/dac2009.html#HanumaiahRVC09 Vinay Hanumaiah Sarma B. K. Vrudhula Karam S. Chatha Performance optimal speed control of multi-core processors under thermal constraints. 1548-1551 2009 DATE https://doi.org/10.1109/DATE.2009.5090908 http://dl.acm.org/citation.cfm?id=1874990 conf/date/2009 db/conf/date/date2009.html#HanumaiahVC09 Vinay Hanumaiah Sarma B. K. Vrudhula Karam S. Chatha Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. 310-313 2009 ICCAD https://doi.org/10.1145/1687399.1687458 https://ieeexplore.ieee.org/document/5361276/ conf/iccad/2009 db/conf/iccad/iccad2009.html#HanumaiahVC09

Sarvesh Bhardwaj Wenping Wang 0004 Rakesh Vattikonda Yu Cao 0001 Sarma B. K. Vrudhula Scalable model for predicting the effect of negative bias temperature instability for reliable design. 361-371 2008 2 IET Circuits Devices Syst. 4 https://doi.org/10.1049/iet-cds:20070225 db/journals/iet-cds/iet-cds2.html#BhardwajWVCV08

Sarvesh Bhardwaj Sarma B. K. Vrudhula Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. 68-80 2008 4 J. Low Power Electron. 1 https://doi.org/10.1166/jolpe.2008.147 db/journals/jolpe/jolpe4.html#BhardwajV08

Sarvesh Bhardwaj Sarma B. K. Vrudhula Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. 445-455 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2008.916341 db/journals/tcad/tcad27.html#BhardwajV08

Sarvesh Bhardwaj Sarma B. K. Vrudhula Amit Goel A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. 1812-1825 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2008.927671 db/journals/tcad/tcad27.html#BhardwajVG08

Kyungsoo Lee Naehyuck Chang Jianli Zhuo Chaitali Chakrabarti Sudheendra Kadri Sarma B. K. Vrudhula A fuel-cell-battery hybrid for portable embedded systems. 2008 13 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/1297666.1297685 db/journals/todaes/todaes13.html#LeeCZCKV08 19:1-19:34

Tejaswi Gowda Sarma B. K. Vrudhula Decomposition based approach for synthesis of multi-level threshold logic circuits. 125-130 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483925 http://dl.acm.org/citation.cfm?id=1356839 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#GowdaV08 Tejaswi Gowda Samuel Leshner Sarma B. K. Vrudhula Seungchan Kim Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. 212-219 2008 BIODEVICES (1) conf/biostec/2008bd1 db/conf/biostec/biodevices2008-1.html#GowdaLVK08 Amit Goel Sarma B. K. Vrudhula Statistical waveform and current source based standard cell models for accurate timing analysis. 227-230 2008 DAC https://doi.org/10.1145/1391469.1391526 conf/dac/2008 db/conf/dac/dac2008.html#GoelV08 Amit Goel Sarma B. K. Vrudhula Current source based standard cell model for accurate signal integrity and timing analysis. 574-579 2008 DATE https://doi.org/10.1109/DATE.2008.4484738 https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484738 https://doi.org/10.1145/1403375.1403515 conf/date/2008 db/conf/date/date2008.html#GoelV08 Ravishankar Rao Sarma B. K. Vrudhula Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. 537-542 2008 ICCAD https://doi.org/10.1109/ICCAD.2008.4681627 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2008.4681627 https://dl.acm.org/citation.cfm?id=1509576 conf/iccad/2008 db/conf/iccad/iccad2008.html#RaoV08 Ravishankar Rao Sarma B. K. Vrudhula Krzysztof S. Berezowski Analytical results for design space exploration of multi-core processors employing thread migration. 229-232 2008 ISLPED https://doi.org/10.1145/1393921.1393981 conf/islped/2008 db/conf/islped/islped2008.html#RaoVB08 Saravanan Ramamoorthy Haibo Wang 0005 Sarma B. K. Vrudhula A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. 123-126 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479711 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.129 conf/isqed/2008 db/conf/isqed/isqed2008.html#RamamoorthyWV08 Amit Goel Sarma B. K. Vrudhula Feroze Taraporevala Praveen Ghanta A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. 200-206 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479726 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.100 conf/isqed/2008 db/conf/isqed/isqed2008.html#GoelVTG08 Deepa Kannan Aviral Shrivastava Vipin Mohan Sarvesh Bhardwaj Sarma B. K. Vrudhula Temperature and Process Variations Aware Power Gating of Functional Units. 515-520 2008 VLSI Design https://doi.org/10.1109/VLSI.2008.83 https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.83 conf/vlsid/2008 db/conf/vlsid/vlsid2008.html#KannanSMBV08 Deepa Kannan Aviral Shrivastava Sarvesh Bhardwaj Sarma B. K. Vrudhula Power Reduction of Functional Units Considering Temperature and Process Variations. 533-539 2008 VLSI Design https://doi.org/10.1109/VLSI.2008.81 https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.81 conf/vlsid/2008 db/conf/vlsid/vlsid2008.html#KannanSBV08

Praveen Ghanta Sarma B. K. Vrudhula Analysis of Power Supply Noise in the Presence of Process Variations. 256-266 2007 24 IEEE Des. Test Comput. 3 https://doi.org/10.1109/MDT.2007.61 http://doi.ieeecomputersociety.org/10.1109/MDT.2007.61 db/journals/dt/dt24.html#GhantaV07

Krzysztof S. Berezowski Sarma B. K. Vrudhula Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. 447-466 2007 13 J. Multiple Valued Log. Soft Comput. 4-6 http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-13-number-4-6-2007/mvlsc-13-4-6-p-447-466/ db/journals/mvl/mvl13.html#BerezowskiV07

Ravishankar Rao Sarma B. K. Vrudhula Energy optimal speed control of a producer-consumer device pair. 2007 6 ACM Trans. Embed. Comput. Syst. 4 https://doi.org/10.1145/1274858.1274868 db/journals/tecs/tecs6.html#RaoV07 30

Ravishankar Rao Sarma B. K. Vrudhula Performance optimal processor throttling under thermal constraints. 257-266 2007 conf/cases/2007 CASES https://doi.org/10.1145/1289881.1289925 db/conf/cases/cases2007.html#RaoV07 Wenping Wang 0004 Shengqi Yang Sarvesh Bhardwaj Rakesh Vattikonda Sarma B. K. Vrudhula Frank Liu 0001 Yu Cao 0001 The Impact of NBTI on the Performance of Combinational and Sequential Circuits. 364-369 2007 conf/dac/2007 DAC https://doi.org/10.1145/1278480.1278573 db/conf/dac/dac2007.html#WangYBVVLC07 Tejaswi Gowda Samuel Leshner Sarma B. K. Vrudhula Goran Konjevod Synthesis of threshold logic circuits using tree matching. 850-853 2007 ECCTD https://doi.org/10.1109/ECCTD.2007.4529730 conf/ecctd/2007 db/conf/ecctd/ecctd2007.html#GowdaLVK07 Tejaswi Gowda Sarma B. K. Vrudhula Goran Konjevod Combinational equivalence checking for threshold logic circuits. 102-107 2007 conf/glvlsi/2007 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1228784.1228813 db/conf/glvlsi/glvlsi2007.html#GowdaVK07 Ravishankar Rao Sarma B. K. Vrudhula Chaitali Chakrabarti Throughput of multi-core processors under thermal constraints. 201-206 2007 ISLPED https://doi.org/10.1145/1283780.1283824 conf/islped/2007 db/conf/islped/islped2007.html#RaoVC07 Krzysztof S. Berezowski Sarma B. K. Vrudhula Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. 24 2007 ISMVL https://doi.org/10.1109/ISMVL.2007.36 https://doi.ieeecomputersociety.org/10.1109/ISMVL.2007.36 conf/ismvl/2007 db/conf/ismvl/ismvl2007.html#BerezowskiV07 Amit Goel Sarvesh Bhardwaj Praveen Ghanta Sarma B. K. Vrudhula Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. 125-137 2007 conf/patmos/2007 PATMOS https://doi.org/10.1007/978-3-540-74442-9_13 db/conf/patmos/patmos2007.html#GoelBGV07 Sarma B. K. Vrudhula Sarvesh Bhardwaj Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. 9 2007 conf/vlsid/2007 VLSI Design https://doi.org/10.1109/VLSID.2007.170 https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.170 db/conf/vlsid/vlsid2007.html#VrudhulaB07 Sarvesh Bhardwaj Sarma B. K. Vrudhula A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. 589-594 2007 conf/vlsid/2007 VLSI Design https://doi.org/10.1109/VLSID.2007.11 https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.11 db/conf/vlsid/vlsid2007.html#BhardwajV07

Praveen Ghanta Sarma B. K. Vrudhula Rajendran Panda Janet Meiling Wang Stochastic Power Grid Analysis Considering Process Variations http://arxiv.org/abs/0710.4649 2007 CoRR abs/0710.4649 db/journals/corr/corr0710.html#abs-0710-4649

Sarvesh Bhardwaj Yu Cao 0001 Sarma B. K. Vrudhula Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. 240-250 2006 2 J. Low Power Electron. 2 https://doi.org/10.1166/jolpe.2006.065 db/journals/jolpe/jolpe2.html#BhardwajCV06

Sarma B. K. Vrudhula Janet Meiling Wang Praveen Ghanta Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. 2001-2011 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2005.862734 db/journals/tcad/tcad25.html#VrudhulaWG06

Ravishankar Rao Sarma B. K. Vrudhula Energy-Optimal Speed Control of a Generic Device. 2737-2746 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2006.882598 db/journals/tcad/tcad25.html#RaoV06

Kaviraj Chopra Sarma B. K. Vrudhula Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. 2820-2832 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2006.882603 db/journals/tcad/tcad25.html#ChopraV06

Tao Shu Marwan Krunz Sarma B. K. Vrudhula Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. 3109-3118 2006 5 IEEE Trans. Wirel. Commun. 11 https://doi.org/10.1109/TWC.2006.04738 db/journals/twc/twc5.html#ShuKV06

Sarvesh Bhardwaj Yu Cao 0001 Sarma B. K. Vrudhula Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. 953-958 2006 conf/aspdac/2006 ASP-DAC https://doi.org/10.1109/ASPDAC.2006.1594809 https://doi.org/10.1145/1118299.1118513 db/conf/aspdac/aspdac2006.html#BhardwajCV06 Sarvesh Bhardwaj Wenping Wang 0004 Rakesh Vattikonda Yu Cao 0001 Sarma B. K. Vrudhula Predictive Modeling of the NBTI Effect for Reliable Design. 189-192 2006 CICC https://doi.org/10.1109/CICC.2006.320885 conf/cicc/2006 db/conf/cicc/cicc2006.html#BhardwajWVCV06 Praveen Ghanta Sarma B. K. Vrudhula Sarvesh Bhardwaj Rajendran Panda Stochastic variational analysis of large power grids considering intra-die correlations. 211-216 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1146966 db/conf/dac/dac2006.html#GhantaVBP06 Jianli Zhuo Chaitali Chakrabarti Naehyuck Chang Sarma B. K. Vrudhula Extending the lifetime of fuel cell based hybrid systems. 562-567 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147056 db/conf/dac/dac2006.html#ZhuoCCV06 Youngjin Cho Naehyuck Chang Chaitali Chakrabarti Sarma B. K. Vrudhula High-level power management of embedded systems with application-specific energy cost functions. 568-573 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147057 db/conf/dac/dac2006.html#ChoCCV06 Sarvesh Bhardwaj Sarma B. K. Vrudhula Praveen Ghanta Yu Cao 0001 Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. 791-796 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147109 db/conf/dac/dac2006.html#BhardwajVGC06 Sarvesh Bhardwaj Praveen Ghanta Sarma B. K. Vrudhula A framework for statistical timing analysis using non-linear delay and slew models. 225-230 2006 conf/iccad/2006 ICCAD https://doi.org/10.1145/1233501.1233546 https://doi.org/10.1109/ICCAD.2006.320140 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2006.320140 db/conf/iccad/iccad2006.html#BhardwajGV06 Ravishankar Rao Sarma B. K. Vrudhula Chaitali Chakrabarti Naehyuck Chang An optimal analytical solution for processor speed control with thermal constraints. 292-297 2006 conf/islped/2006 ISLPED https://doi.org/10.1145/1165573.1165643 db/conf/islped/islped2006.html#RaoVCC06 Jianli Zhuo Chaitali Chakrabarti Naehyuck Chang Sarma B. K. Vrudhula Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. 424-429 2006 conf/islped/2006 ISLPED https://doi.org/10.1145/1165573.1165676 db/conf/islped/islped2006.html#ZhuoCCV06 Praveen Ghanta Sarma B. K. Vrudhula Variational Interconnect Delay Metrics for Statistical Timing Analysis. 19-24 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.143 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.143 db/conf/isqed/isqed2006.html#GhantaV06 Sarvesh Bhardwaj Yu Cao 0001 Sarma B. K. Vrudhula LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. 717-722 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.83 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.83 db/conf/isqed/isqed2006.html#BhardwajCV06

Sarvesh Bhardwaj Sarma B. K. Vrudhula David T. Blaauw Probability distribution of signal arrival times using Bayesian networks. 1784-1794 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2005.852436 db/journals/tcad/tcad24.html#BhardwajVB05

Sarvesh Bhardwaj Sarma B. K. Vrudhula Leakage minimization of nano-scale circuits in the presence of systematic and random variations. 541-546 2005 conf/dac/2005 DAC https://doi.org/10.1145/1065579.1065719 db/conf/dac/dac2005.html#BhardwajV05 Ravishankar Rao Sarma B. K. Vrudhula Energy optimal speed control of devices with discrete speed sets. 901-904 2005 conf/dac/2005 DAC https://doi.org/10.1145/1065579.1065815 db/conf/dac/dac2005.html#RaoV05 Praveen Ghanta Sarma B. K. Vrudhula Rajendran Panda Janet Meiling Wang Stochastic Power Grid Analysis Considering Process Variations. 964-969 2005 conf/date/2005 DATE https://doi.org/10.1109/DATE.2005.282 https://doi.ieeecomputersociety.org/10.1109/DATE.2005.282 http://dl.acm.org/citation.cfm?id=1049254 db/conf/date/date2005.html#GhantaVPW05 Krzysztof S. Berezowski Sarma B. K. Vrudhula Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. 139-143 2005 conf/dsd/2005 DSD https://doi.org/10.1109/DSD.2005.21 https://doi.ieeecomputersociety.org/10.1109/DSD.2005.21 db/conf/dsd/dsd2005.html#BerezowskiV05 Ravishankar Rao Sarma B. K. Vrudhula Battery optimization vs energy optimization: which to choose and when? 439-445 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#RaoV05 https://doi.org/10.1109/ICCAD.2005.1560108 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560108 http://dl.acm.org/citation.cfm?id=1129664 Sarvesh Bhardwaj Sarma B. K. Vrudhula Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. 713-718 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#BhardwajV05 https://doi.org/10.1109/ICCAD.2005.1560158 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560158 http://dl.acm.org/citation.cfm?id=1129703 Tao Shu Marwan Krunz Sarma B. K. Vrudhula Power balanced coverage-time optimization for clustered wireless sensor networks. 111-120 2005 conf/mobihoc/2005 MobiHoc https://doi.org/10.1145/1062689.1062705 db/conf/mobihoc/mobihoc2005.html#ShuKV05 Ravishankar Rao Sarma B. K. Vrudhula Musaravakkam S. Krishnan Disk drive energy optimization for audio-video applications. 93-103 2004 conf/cases/2004 CASES https://doi.org/10.1145/1023833.1023848 db/conf/cases/cases2004.html#RaoVK04 Kanak Agarwal 0001 Dennis Sylvester David T. Blaauw Frank Liu 0001 Sani R. Nassif Sarma B. K. Vrudhula Variational delay metrics for interconnect timing analysis. 381-384 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996675 db/conf/dac/dac2004.html#AgarwalSBLNV04 Sreeja Raj Sarma B. K. Vrudhula Janet Meiling Wang A methodology to improve timing yield in the presence of process variations. 448-453 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996694 db/conf/dac/dac2004.html#RajVW04 Kaviraj Chopra Sarma B. K. Vrudhula Implicit pseudo boolean enumeration algorithms for input vector control. 767-772 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996774 db/conf/dac/dac2004.html#ChopraV04 Sridhar Dasika Sarma B. K. Vrudhula Kaviraj Chopra R. Srinivasan A Framework for Battery-Aware Sensor Management. 962-967 2004 conf/date/2004 DATE https://doi.org/10.1109/DATE.2004.1269017 https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269017 http://dl.acm.org/citation.cfm?id=969166 db/conf/date/date2004-2.html#DasikaVCS04 Ravishankar Rao Sarma B. K. Vrudhula Energy optimization for a two-device data flow chain. 268-274 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382585 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382585 https://dl.acm.org/citation.cfm?id=1112287 db/conf/iccad/iccad2004.html#RaoV04 Janet Meiling Wang Praveen Ghanta Sarma B. K. Vrudhula Stochastic analysis of interconnect performance in the presence of process variations. 880-886 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382698 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382698 https://dl.acm.org/citation.cfm?id=1112373 db/conf/iccad/iccad2004.html#WangGV04 Kaviraj Chopra Sarma B. K. Vrudhula Sarvesh Bhardwaj Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. 240- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260931 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260931 db/conf/vlsid/vlsid2004.html#ChopraVB04 Raghukiran Sreeramaneni Sarma B. K. Vrudhula Energy Profiler for Hardware/Software Co-Design. 335- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260945 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260945 db/conf/vlsid/vlsid2004.html#SreeramaneniV04

Ravishankar Rao Sarma B. K. Vrudhula Daler N. Rakhmatov Battery Modeling for Energy-Aware System Design. 77-87 2003 36 Computer 12 https://doi.org/10.1109/MC.2003.1250886 http://doi.ieeecomputersociety.org/10.1109/MC.2003.1250886 db/journals/computer/computer36.html#RaoVR03

Sarma B. K. Vrudhula David T. Blaauw Supamas Sirichotiyakul Probabilistic analysis of interconnect coupling noise. 1188-1203 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/TCAD.2003.816212 db/journals/tcad/tcad22.html#VrudhulaBS03

Daler N. Rakhmatov Sarma B. K. Vrudhula Energy management for battery-powered embedded systems. 277-324 2003 2 ACM Trans. Embed. Comput. Syst. 3 https://doi.org/10.1145/860176.860179 db/journals/tecs/tecs2.html#RakhmatovV03

Daler N. Rakhmatov Sarma B. K. Vrudhula Deborah A. Wallach A model for battery lifetime analysis for organizing applications on a pocket computer. 1019-1030 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2003.819320 https://www.wikidata.org/entity/Q62580428 db/journals/tvlsi/tvlsi11.html#RakhmatovVW03

Aseem Agarwal David T. Blaauw Vladimir Zolotov Sarma B. K. Vrudhula Computation and Refinement of Statistical Bounds on Circuit Delay. 348-353 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.775922 db/conf/dac/dac2003.html#AgarwalBZV03 Aseem Agarwal David T. Blaauw Vladimir Zolotov Sarma B. K. Vrudhula Statistical Timing Analysis Using Bounds. 10062-10067 2003 conf/date/2003 DATE https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10196 http://dl.acm.org/citation.cfm?id=1022706 db/conf/date/date2003.html#AgarwalBZV03 Sarvesh Bhardwaj Sarma B. K. Vrudhula David T. Blaauw AU: Timing Analysis Under Uncertainty. 615-620 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257874 https://dl.acm.org/citation.cfm?id=1009953 db/conf/iccad/iccad2003.html#BhardwajVB03 Ravishankar Rao Sarma B. K. Vrudhula Daler N. Rakhmatov Analysis of discharge techniques for multiple battery systems. 44-47 2003 conf/islped/2003 ISLPED https://doi.org/10.1145/871506.871521 db/conf/islped/islped2003.html#RaoVR03

Qi Wang Sarma B. K. Vrudhula Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. 306-318 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.986424 db/journals/tcad/tcad21.html#WangV02

Haibo Wang 0005 Sarma B. K. Vrudhula Behavioral synthesis of field programmable analog array circuits. 563-604 2002 7 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/605440.605445 db/journals/todaes/todaes7.html#WangV02

Daler N. Rakhmatov Sarma B. K. Vrudhula Hardware-software bipartitioning for dynamically reconfigurable systems. 145-150 2002 conf/codes/2002 CODES https://doi.org/10.1145/774789.774819 db/conf/codes/codes2002.html#RakhmatovV02 Daler N. Rakhmatov Sarma B. K. Vrudhula Chaitali Chakrabarti Battery-conscious task sequencing for portable devices including voltage/clock scaling. 189-194 2002 conf/dac/2002 DAC https://doi.org/10.1145/513918.513967 db/conf/dac/dac2002.html#RakhmatovVC02 Sarma B. K. Vrudhula David T. Blaauw Supamas Sirichotiyakul Estimation of the likelihood of capacitive coupling noise. 653-658 2002 conf/dac/2002 DAC https://doi.org/10.1145/513918.514085 db/conf/dac/dac2002.html#VrudhulaBS02 Sarvesh Bhardwaj Sarma B. K. Vrudhula David T. Blaauw Estimation of signal arrival times in the presence of delay noise. 418-422 2002 conf/iccad/2002 ICCAD https://doi.org/10.1145/774572.774634 https://doi.org/10.1109/ICCAD.2002.1167567 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167567 db/conf/iccad/iccad2002.html#BhardwajVB02 Daler N. Rakhmatov Sarma B. K. Vrudhula Deborah A. Wallach Battery lifetime prediction for energy-aware computing. 154-159 2002 conf/islped/2002 ISLPED https://doi.org/10.1145/566408.566449 db/conf/islped/islped2002.html#RakhmatovVW02 Aseem Agarwal David T. Blaauw Vladimir Zolotov Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. 16-21 2002 conf/tau/2002 Timing Issues in the Specification and Synthesis of Digital Systems https://doi.org/10.1145/589411.589415 db/conf/tau/tau2002.html#AgarwalBZV02 Aseem Agarwal David T. Blaauw Vladimir Zolotov Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. 29-36 2002 conf/tau/2002 Timing Issues in the Specification and Synthesis of Digital Systems https://doi.org/10.1145/589411.589417 db/conf/tau/tau2002.html#AgarwalBZV02a Daler N. Rakhmatov Sarma B. K. Vrudhula An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. 488-493 2001 conf/iccad/2001 ICCAD https://doi.org/10.1109/ICCAD.2001.968687 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2001.968687 http://dl.acm.org/citation.cfm?id=603196 db/conf/iccad/iccad2001.html#RakhmatovV01 Daler N. Rakhmatov Sarma B. K. Vrudhula Minimizing routing configuration cost in dynamically reconfigurable FPGAs. 145 2001 conf/ipps/2001 IPDPS db/conf/ipps/ipdps2001.html#RakhmatovV01 https://doi.org/10.1109/IPDPS.2001.925132 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2001.925132 Daler N. Rakhmatov Sarma B. K. Vrudhula Time-to-failure estimation for batteries in portable electronic systems. 88-91 2001 conf/islped/2001 ISLPED https://doi.org/10.1145/383082.383101 db/conf/islped/islped2001.html#RakhamtovV01

Daler N. Rakhmatov Sarma B. K. Vrudhula Thomas J. Brown Ajay Nagarandal Adaptive Multiuser Online Reconfigurable Engine. 53-67 2000 17 IEEE Des. Test Comput. 1 https://doi.org/10.1109/54.825677 http://doi.ieeecomputersociety.org/10.1109/54.825677 db/journals/dt/dt17.html#RakhmatovVBN00

Qi Wang Sarma B. K. Vrudhula Gary K. H. Yeap Shantanu Ganguly Power reduction and power-delay trade-offs using logic transformations. 97-121 1999 4 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/298865.298872 db/journals/todaes/todaes4.html#WangVYG99

Qi Wang Sarma B. K. Vrudhula An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. 556-562 1999 conf/iccd/1999 ICCD https://doi.org/10.1109/ICCD.1999.808595 https://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808595 db/conf/iccd/iccd1999.html#WangV99

Hong-Yu Xie Sarma B. K. Vrudhula A Technique for Estimating Signal Activity in Logic Circuits. 141-152 1998 5 Integr. Comput. Aided Eng. 2 https://doi.org/10.3233/ica-1998-5205 db/journals/icae/icae5.html#XieV98

Qi Wang Sarma B. K. Vrudhula Data Driven Power Optimization of Sequential Circuits. 686-691 1998 conf/date/1998 DATE https://doi.org/10.1109/DATE.1998.655932 https://doi.ieeecomputersociety.org/10.1109/DATE.1998.655932 http://dl.acm.org/citation.cfm?id=368335 db/conf/date/date1998.html#WangV98 Qi Wang Sarma B. K. Vrudhula Static power optimization of deep submicron CMOS circuits for dual VT technology. 490-496 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.289076 https://doi.org/10.1109/ICCAD.1998.742957 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742957 db/conf/iccad/iccad1998.html#WangV98 Qi Wang Sarma B. K. Vrudhula On short circuit power estimation of CMOS inverters. 70-75 1998 conf/iccd/1998 ICCD https://doi.org/10.1109/ICCD.1998.727025 https://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727025 db/conf/iccd/iccd1998.html#WangV98 Qi Wang Sarma B. K. Vrudhula Shantanu Ganguly An Investigation of Power Delay Trade-Offs on PowerPC Circuits. 425-428 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266190 db/conf/dac/dac97.html#WangVG97 K. McCarley Sarma B. K. Vrudhula Macro-instruction generation for dynamic logic caching. 63-69 1997 IEEE International Workshop on Rapid System Prototyping https://doi.org/10.1109/IWRSP.1997.618827 https://doi.ieeecomputersociety.org/10.1109/IWRSP.1997.618827 conf/rsp/1997 db/conf/rsp/rsp1997.html#McCarleyV97 E. Tsun Sarma B. K. Vrudhula Rapid prototyping of networks of asynchronous multiple functional units. 157-166 1997 IEEE International Workshop on Rapid System Prototyping https://doi.org/10.1109/IWRSP.1997.618892 https://doi.ieeecomputersociety.org/10.1109/IWRSP.1997.618892 conf/rsp/1997 db/conf/rsp/rsp1997.html#TsunV97

Yung-Te Lai Massoud Pedram Sarma B. K. Vrudhula Formal Verification Using Edge-Valued Binary Decision Diagrams. 247-255 1996 45 IEEE Trans. Computers 2 db/journals/tc/tc45.html#LaiPV96 https://doi.org/10.1109/12.485378 http://doi.ieeecomputersociety.org/10.1109/12.485378

Qi Wang Sarma B. K. Vrudhula Multi-level logic optimization for low power using local logic transformations. 270-277 1996 conf/iccad/1996 ICCAD https://doi.org/10.1109/ICCAD.1996.569643 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1996.569643 https://dl.acm.org/citation.cfm?id=244569 db/conf/iccad/iccad1996.html#WangV96

Amitava Majumdar 0001 Sarma B. K. Vrudhula Fault Coverage and Test Length Estimation for Random Pattern Testing. 234-247 1995 44 IEEE Trans. Computers 2 db/journals/tc/tc44.html#MajumdarV95 https://doi.org/10.1109/12.364535 http://doi.ieeecomputersociety.org/10.1109/12.364535

Amitava Majumdar 0001 Sarma B. K. Vrudhula Techniques for estimating test length under random test. 285-297 1994 5 J. Electron. Test. 2-3 https://doi.org/10.1007/BF00972088 db/journals/et/et5.html#MajumdarV94

Yung-Te Lai Massoud Pedram Sarma B. K. Vrudhula EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. 959-975 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/43.298033 db/journals/tcad/tcad13.html#LaiPV94

King C. Ho Sarma B. K. Vrudhula Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. 1201-1222 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/43.317463 db/journals/tcad/tcad13.html#HoV94

T.-Y. Wuu Sarma B. K. Vrudhula A design of a fast and area efficient multi-input Muller C-element. 215-219 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.238414 db/journals/tvlsi/tvlsi1.html#WuuV93

Amitava Majumdar 0001 Sarma B. K. Vrudhula Analysis of signal probability in logic circuits using stochastic models. 365-379 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/92.238448 db/journals/tvlsi/tvlsi1.html#MajumdarV93

Yung-Te Lai Massoud Pedram Sarma B. K. Vrudhula BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. 642-647 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.165078 db/conf/dac/dac93.html#LaiPV93 Yung-Te Lai Massoud Pedram Sarma B. K. Vrudhula FGILP: an integer linear program solver based on function graphs. 685-689 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580162 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580162 https://dl.acm.org/citation.cfm?id=259903 db/conf/iccad/iccad1993.html#LaiPV93 Aseem Agarwal Kanak Agarwal 0001 Pei An Akhil Arunkumar Elham Azari Mohammad Farhadi Bajestani Michael A. Baker Hugh J. Barnaby Krzysztof S. Berezowski Vineeth Bharadwaj Sarvesh Bhardwaj David T. Blaauw Thomas J. Brown Yu Cao 0001 Matteo Cavaliere Chaitali Chakrabarti Gayathri Chalivendra Vikas Chandra Naehyuck Chang Karam S. Chatha Pai-Yu Chen W. Chen Vidya A. Chhabria Youngjin Cho Kaviraj Chopra Jennifer Blain Christen Pravin Dalale Ganesh Dasika Sridhar Dasika Joseph Davis Aykut Dengi Digant Desai Ayushi Dube Mohammad Farhadi Shantanu Ganguly Benjamin Gaudette Praveen Ghanta Mehdi Ghasemi 0003 Amit Goel Nakul Gopalan Tejaswi Gowda Mahdi Hamzeh Vinay Hanumaiah Soroush Heidari King C. Ho Tuo-Hung Hou Mehmet Ince Reiley Jeyapaul Deepak Kadetotad Sudheendra Kadri Deepa Kannan Sunil P. Khatri Gyudong Kim Minkyu Kim 0001 Seungchan Kim Seungryong Kim Younggeun Kim 0001Young Geun Kim 0001 Goran Konjevod Michael N. Kozicki Musaravakkam S. Krishnan Marwan Krunz Niranjan Kulkarni Sanmukh R. Kuppannagari Yung-Te Lai Aaron Lamb Cheng-Yen Lee Kyungsoo Lee Samuel Leshner Binbin Lin Frank Liu 0001 Wei Liu 0016 Yufei Ma 0002 Debayan Mahalanabis Amitava Majumdar 0001 Nikhil Matkar K. McCarley Vipin Mohan Abinash Mohanty Ajay Nagarandal Alberto Nannarelli Sani R. Nassif Nishant Nukala Sule Ozev Jared Pager Rajendran Panda Saurabh Patel Omkar Patil Massoud Pedram Sreeja Raj Daler N. Rakhmatov Saravanan Ramamoorthy Ravishankar Rao Janet RovedaJanet Meiling Wang Sachin S. Sapatnekar Kyler R. Scott Jae-sun SeoJae-Sun Seo S. Shah Davesh Shingari Aviral Shrivastava Tao Shu Gian Singh Supamas Sirichotiyakul M. Sivaraj Raghukiran Sreeramaneni R. Srinivasan Naveen Suda Chetan Choppali Sudarshan Dennis Sylvester Feroze Taraporevala E. Tsun Rakesh Vattikonda Ankit Wagle Deborah A. Wallach Haibo Wang 0005 I-Ting Wang Qi Wang Wenping Wang 0004 Andreas Thor Winther Carole-Jean Wu T.-Y. Wuu Hong-Yu Xie Zihan Xu Jinghua Yang Shengqi Yang Yezhou Yang Xiaoyin Yao Jieping Ye Gary K. H. Yeap Shimeng Yu Tu Zheng Jianli Zhuo Vladimir Zolotov