Jian-Hsing Lee

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shao-Chang Huang

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Publications

2023
[c21]
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Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Chien-Wei Wang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Kuan-I Ho, Che-Hua Chang, Hsiao-Ying Yang, Chung-Ren Lao, Jian-Hsing Lee, Ke-Horng Chen:
Optimizing Device Metal Routing Layouts by the Simulation Tool. ICCE-Taiwan 2023: 219-220
[c20]
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Shao-Chang Huang, Kai-Chieh Hsu, Chih-Hsuan Lin, Chien-Wei Wang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen:
Bipolar Transistors' Holding Phenomena. ICCE-Taiwan 2023: 221-222
[c19]
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Shao-Chang Huang, Chien-Wei Wang, Chih-Hsuan Lin, Kai-Chieh Hsu, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen:
Transmission Line Pulse Width Impacting on Device Performances. ICCE-Taiwan 2023: 227-228
[c18]
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Jian-Hsing Lee, Gong-Kai Lin, Chun-Chih Chen, Li-Fan Chen, Chien-Wei Wang, Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Ke-Horng Chen:
A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor. IRPS 2023: 1-6
2022
[c17]
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Shao-Chang Huang, Jian-Hsing Lee, Chun-Chih Chen, Ching-Ho Li, Chih-Cherng Liao, Kai-Chieh Hsu, Gong-Kai Lin, Li-Fan Chen, Chien-Wei Wang, Chih-Hsuan Lin, Yeh-Ning Jou, Ke-Horng Chen:
Gate Voltages Impacting on Latch-up Measurements. ICCE-TW 2022: 75-76
[c16]
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Shao-Chang Huang, Jian-Hsing Lee, Ching-Ho Li, Sue-Yi Chen, Chih-Hsuan Lin, Chun-Chih Chen, Li-Fan Chen, Gong-Kai Lin, Chien-Wei Wang, Kai-Chieh Hsu, Szu-Chi Chen, Shang-Chuan Pai, Fu-Wei Pai, Yin-Wei Peng, Chih-Cherng Liao, Ke-Horng Chen:
EOS Endurance Power Circuits without Depletion Mode Devices. ICCE-TW 2022: 79-80
2021
[c14]
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Shao-Chang Huang, Yu-Yung Kao, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Ke-Horng Chen:
Signal Control Switching Applied on Large Array Devices' Layouts. ICCE-TW 2021: 1-2
[c13]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee:
Optimizing Power IC Layouts by Simulation Tools. ICCE-TW 2021: 1-2
2020
[c11]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen:
The Correlations between ESD and TLP in Large Array Devices. ICCE-TW 2020: 1-2
[c10]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Chih-Hsuan Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen:
Signal Control Switching for Improving Large Array Devices' ESD Performances. ICCE-TW 2020: 1-2
2019
[c9]
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  - conf/icce-tw/HuangLLWNWCCJL19
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Shao-Chang Huang, Chih-Cherng Liao, Hsien-Feng Liao, Shou-Peng Weng, Karuna Nidhi, Yu-Kai Wang, Yi-Jen Chen, Hwa-Chyi Chiou, Yeh-Ning Jou, Jian-Hsing Lee:
Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. ICCE-TW 2019: 1-2

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