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ORCIDKwang-Hyun Baek
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Publications
- 2014
[j21]Taegeun Yoo, Hong Chang Yeoh, Yun-Hwan Jung, Seong Jin Cho, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek
:
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS. IEEE J. Solid State Circuits 49(12): 2976-2989 (2014)- [c21]Taegeun Yoo, Yun-Hwan Jung, Hong Chang Yeoh, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek:
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS. ISSCC 2014: 364-365 - 2008
- [c15]Jae-Jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang:
Design of a 6 bit 1.25 GS/s DAC for WPAN. ISCAS 2008: 2262-2265 - 2005
- [j1]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 992-996 (2005) - 2004
- [c10]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ISCAS (2) 2004: 781-784 - 2003
- [c8]Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang:
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. ISCAS (1) 2003: 901-904 - [c7]Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. ISVLSI 2003: 80-86 - [c6]Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. VLSI Design 2003: 261- - 2002
- [c5]Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. ISCAS (5) 2002: 53-56 - 2001
- [c4]Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) 2001: 938-941 - 2000
- [c3]Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 - [c2]Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ICCD 2000: 59-64 - [c1]Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS 2000: 756-759
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