Puneet Sareen

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Markus Dietl

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Publications

2017
[c6]
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Jens Anders, Sebastian Bader, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns:
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. A-SSCC 2017: 325-328
2015
[c5]
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  - conf/norchip/FahmyDSOA15
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S. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders:
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter. NORCAS 2015: 1-4
2012
[c4]
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  - conf/norchip/YogeshSDD12
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Mitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan:
A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter. NORCHIP 2012: 1-4
2011
[c3]
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  - conf/glvlsi/DietlS11
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Markus Dietl, Puneet Sareen:
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications. ACM Great Lakes Symposium on VLSI 2011: 363-366
[c2]
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  - conf/norchip/ElangovanDS11
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Vivek Elangovan, Markus Dietl, Puneet Sareen:
Very high bandwidth semi-digital PLL with large operating frequency range. NORCHIP 2011: 1-6
2010
[c1]
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  - conf/nesea/DietlS10
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Markus Dietl, Puneet Sareen:
Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance. NESEA 2010: 1-4

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