Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing.

Konstantin Moiseev

Konstantin Moiseev Shmuel Wimer Avinoam Kolodny Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. 116-128 2015 48 Integr. https://doi.org/10.1016/j.vlsi.2014.03.002 db/journals/integration/integration48.html#MoiseevWK15

Konstantin Moiseev Avinoam Kolodny Shmuel Wimer The complexity of VLSI power-delay optimization by interconnect resizing. 292-300 2012 23 J. Comb. Optim. 2 https://doi.org/10.1007/s10878-010-9355-1 db/journals/jco/jco23.html#MoiseevKW12

Konstantin Moiseev Avinoam Kolodny Shmuel Wimer Interconnect Bundle Sizing Under Discrete Design Rules. 1650-1654 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2010.2051633 db/journals/tcad/tcad29.html#MoiseevKW10

Konstantin Moiseev Avinoam Kolodny Shmuel Wimer Interconnect power and delay optimization by dynamic programming in gridded design rules. 153-160 2010 ISPD https://doi.org/10.1145/1735023.1735061 https://www.wikidata.org/entity/Q130975493 conf/ispd/2010 db/conf/ispd/ispd2010.html#MoiseevKW10

Konstantin Moiseev Avinoam Kolodny Shmuel Wimer Power-delay optimization in VLSI microprocessors by wire spacing. 2009 14 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/1562514.1562523 https://www.wikidata.org/entity/Q130953889 db/journals/todaes/todaes14.html#MoiseevKW09 55:1-55:28

Konstantin Moiseev Shmuel Wimer Avinoam Kolodny On optimal ordering of signals in parallel wire bundles. 253-268 2008 41 Integr. 2 https://doi.org/10.1016/j.vlsi.2007.06.002 db/journals/integration/integration41.html#MoiseevWK08

Konstantin Moiseev Avinoam Kolodny Shmuel Wimer Timing-aware power-optimal ordering of signals. 2008 13 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/1391962.1391973 https://www.wikidata.org/entity/Q130978707 db/journals/todaes/todaes13.html#MoiseevKW08 65:1-65:17

Shmuel Wimer Shay Michaely Konstantin Moiseev Avinoam Kolodny Optimal bus sizing in migration of processor design. 1089-1100 2006 53-I IEEE Trans. Circuits Syst. I Regul. Pap. 5 https://doi.org/10.1109/TCSI.2006.869902 db/journals/tcas/tcasI53.html#WimerMMK06

Konstantin Moiseev Shmuel Wimer Avinoam Kolodny Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692589 db/conf/iscas/iscas2006.html#MoiseevWK06 Avinoam Kolodny Shay Michaely Shmuel Wimer