112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors.

David Levacq Adem Coskun Salvatore D'Addio Richard Jansen David Levacq Piero Angeletti 112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors. 431-434 2024 MeditCom https://doi.org/10.1109/MeditCom61057.2024.10621245 conf/meditcom/2024 db/conf/meditcom/meditcom2024.html#CoskunDJLA24 streams/conf/meditcom

David Levacq Makoto Takamiya Takayasu Sakurai Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. 2390-2395 2008 43 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2008.2004528 db/journals/jssc/jssc43.html#LevacqTS08

Yasumi Nakamura David Levacq Limin Xiao Takuya Minakawa Taro Niiyama Makoto Takamiya Takayasu Sakurai 1/5 power reduction by global optimization based on fine-grained body biasing. 547-550 2008 CICC https://doi.org/10.1109/CICC.2008.4672143 conf/cicc/2008 db/conf/cicc/cicc2008.html#NakamuraLXMNTS08

David Levacq Vincent Dessard Denis Flandre Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. 689-702 2007 42 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/JSSC.2006.891494 db/journals/jssc/jssc42.html#LevacqDF07

David Bol Ilham Hassoune David Levacq Denis Flandre Jean-Didier Legat Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. 61-78 2007 13 J. Multiple Valued Log. Soft Comput. 1-2 http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-13-number-1-2-2007/mvlsc-13-1-2-p-61-78/ db/journals/mvl/mvl13.html#BolHLFL07

David Levacq Takuya Minakawa Makoto Takamiya Takayasu Sakurai A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. 257-260 https://doi.org/10.1109/CICC.2007.4405727 2007 CICC conf/cicc/2007 db/conf/cicc/cicc2007.html#LevacqMTS07 David Levacq Muhammad Yazid Hiroshi Kawaguchi 0001 Makoto Takamiya Takayasu Sakurai Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. 190-193 2007 ESSCIRC https://doi.org/10.1109/ESSCIRC.2007.4430277 conf/esscirc/2007 db/conf/esscirc/esscirc2007.html#LevacqYKTS07 David Levacq Vincent Dessard Denis Flandre Ultra-low power flip-flops for MTCMOS circuits. 4681-4684 2005 conf/iscas/2005 ISCAS (5) https://doi.org/10.1109/ISCAS.2005.1465677 db/conf/iscas/iscas2005-5.html#LevacqDF05 Piero Angeletti David Bol Adem Coskun Salvatore D'Addio Vincent Dessard Denis Flandre Ilham Hassoune Richard Jansen Hiroshi Kawaguchi 0001 Jean-Didier Legat Takuya Minakawa Yasumi Nakamura Taro Niiyama Takayasu Sakurai Makoto Takamiya Limin Xiao Muhammad Yazid