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Shang Liu 0006

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Qijun Zhang

> Home > Persons > Shang Liu 0006

Publications

2026
[c14]
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Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie:
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. ASP-DAC 2026: 1223-1229
[i19]
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  - journals/corr/abs-2601-01765
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Yao Lu, Shang Liu, Hangan Zhou, Wenji Fang, Qijun Zhang, Zhiyao Xie:
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization. CoRR abs/2601.01765 (2026)
[i16]
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  - journals/corr/abs-2605-15645
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Mengming Li, Chenlu Miao, Buqing Xu, Qijun Zhang, Xiangfeng Sun, Ceyu Xu, Yuan Xie, Wenkai Li, Shang Liu, Zhiyao Xie:
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses. CoRR abs/2605.15645 (2026)
2025
[j2]
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  - journals/tcad/FangLLZXWZX25
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Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 200-213 (2025)
[j1]
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Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(4): 1448-1461 (2025)
[c12]
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Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie:
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. ASP-DAC 2025: 527-533
[c5]
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Qijun Zhang, Yao Lu, Mengming Li, Shang Liu, Zhiyao Xie:
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design. NeurIPS 2025
[i8]
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  - journals/corr/abs-2512-06854
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Qijun Zhang, Yao Lu, Mengming Li, Shang Liu, Zhiyao Xie:
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design. CoRR abs/2512.06854 (2025)
[i7]
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  - journals/corr/abs-2512-14172
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Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie:
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. CoRR abs/2512.14172 (2025)
2024
[c4]
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Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. ASPDAC 2024: 722-727
2023
[c1]
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Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9
[i3]
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  - journals/corr/abs-2308-05345
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Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. CoRR abs/2308.05345 (2023)
[i2]
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  - journals/corr/abs-2311-08441
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Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023)
[i1]
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  - journals/corr/abs-2312-08617
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Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023)

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Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.