<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/fpl/MaSCSV16" mdate="2022-08-16">
<author>Yufei Ma 0002</author>
<author>Naveen Suda</author>
<author orcid="0000-0001-6968-1180">Yu Cao 0001</author>
<author>Jae-sun Seo</author>
<author>Sarma B. K. Vrudhula</author>
<title>Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.</title>
<pages>1-8</pages>
<year>2016</year>
<booktitle>FPL</booktitle>
<ee>https://doi.org/10.1109/FPL.2016.7577356</ee>
<crossref>conf/fpl/2016</crossref>
<url>db/conf/fpl/fpl2016.html#MaSCSV16</url>
</inproceedings>
</dblp>
