Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE.

Trio Adiono Marvin Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE. 792-797 2012 ISPACS https://doi.org/10.1109/ISPACS.2012.6473599 conf/ispacs/2012 db/conf/ispacs/ispacs2012.html#AdionoM12