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"Reverse Engineering RTL Models from DSP Slices in FPGA Netlists."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Avinash Hegde Kota et al. (2026)

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DOI: 10.1109/ISQED69900.2026.11534664

access: closed

type: Conference or Workshop Paper

metadata version: 2026-07-02

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  dblp key:
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  - https://dblp.org/rec/conf/isqed/KotaVVE26
Avinash Hegde Kota, Aparajithan Nathamuni Venkatesan, Ranga Vemuri, John Marty Emmert:
Reverse Engineering RTL Models from DSP Slices in FPGA Netlists. ISQED 2026: 1-6

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last updated on 2026-07-02 20:51 CEST by the dblp team

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