"28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage ..."

Lukas Kull et al. (2017)

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DOI: 10.1109/ISSCC.2017.7870467

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC 2017: 474-475

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