"Design for Bit Error Rate estimation of high speed serial links."

Ujjwal Guin, Chen-Huan Chiang (2011)

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DOI: 10.1109/VTS.2011.5783734

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Ujjwal Guin, Chen-Huan Chiang:
Design for Bit Error Rate estimation of high speed serial links. VTS 2011: 278-283

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