<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<article key="journals/iet-cdt/SasakiIHKK08" mdate="2020-07-14">
<author>Takahiro Sasaki</author>
<author>Yuji Ichikawa</author>
<author>Tetsuo Hironaka</author>
<author>Toshiaki Kitamura</author>
<author>Toshio Kondo</author>
<title>Evaluation of low-energy and high-performance processor using variable stages pipeline technique.</title>
<pages>230-238</pages>
<year>2008</year>
<volume>2</volume>
<journal>IET Comput. Digit. Tech.</journal>
<number>3</number>
<ee>https://doi.org/10.1049/iet-cdt:20070130</ee>
<url>db/journals/iet-cdt/iet-cdt2.html#SasakiIHKK08</url>
</article></dblp>
