MCRA: Multicolumn Residue Accumulation Analog Compute-in-Memory Architecture With Time-Domain M-Input ΣΔ ADC.

Xinyu Li Wenlun Zhang Shimpei Ando Zhongfeng Wang 0001 Jun Lin 0001 Kentaro Yoshioka MCRA: Multicolumn Residue Accumulation Analog Compute-in-Memory Architecture With Time-Domain M-Input ΣΔ ADC. 2026 May 1556-1566 34 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2026.3665471 db/journals/tvlsi/tvlsi34.html#LiZAWLY26 streams/journals/tvlsi