VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies.

Preetham Lakshmikanthan

Preetham Lakshmikanthan Adrian Nunez VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies. 10-16 2007 35 SIGARCH Comput. Archit. News 5 https://doi.org/10.1145/1360464.1360471 db/journals/sigarch/sigarch35.html#LakshmikanthanN07

Preetham Lakshmikanthan Adrian Nunez A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. 614-623 2006 conf/patmos/2006 PATMOS https://doi.org/10.1007/11847083_60 db/conf/patmos/patmos2006.html#LakshmikanthanN06 Preetham Lakshmikanthan Karan Sahni Adrian Nunez Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology. 93-94 2006 SoCC https://doi.org/10.1109/SOCC.2006.283854 conf/socc/2006 db/conf/socc/socc2006.html#LakshmikanthanSN06 Preetham Lakshmikanthan Siddharth Mulchandani Adrian Nunez Robust simple hyperstable adaptive recursive algorithms. 243-248 2004 conf/iastedCCS/2004 Circuits, Signals, and Systems db/conf/iastedCCS/iastedCCS2004.html#LakshmikanthanMN04 Preetham Lakshmikanthan Sriram Govindarajan Vinoo Srinivasan Ranga Vemuri Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. 924-931 2000 conf/ipps/2000w IPDPS Workshops https://doi.org/10.1007/3-540-45591-4_127 db/conf/ipps/ipdpsW2000.html#LakshmikanthanGSV00 Sriram Govindarajan Vinoo Srinivasan Preetham Lakshmikanthan Ranga Vemuri A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. 212-219 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812611 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812611 db/conf/vlsid/vlsid2000.html#GovindarajanSLV00 Sriram Govindarajan Siddharth Mulchandani Adrian Nunez Karan Sahni Vinoo Srinivasan Ranga Vemuri