ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge.

Jian-Yi Meng Jianyi Meng

Yifan Zhao 0007 Honglin Kuang Xinglong Yu Yi Sun Ziyi Hao Jianyi Meng Jun Han 0003 ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge. 7030-7043 2025 November 72 IEEE Trans. Circuits Syst. I Regul. Pap. 11 https://doi.org/10.1109/TCSI.2025.3568116 db/journals/tcasI/tcasI72.html#ZhaoKYSHMH25 streams/journals/tcasI

Yifan Zhao 0007 Honglin Kuang Yi Sun Zhen Yang Chen Chen 0058 Jianyi Meng Jun Han 0003 Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. 10-17 2023 ASAP https://doi.org/10.1109/ASAP57973.2023.00014 conf/asap/2023 db/conf/asap/asap2023.html#ZhaoKSYCMH23 Zhaoyang Du Yijin Guan Tianchan Guan Dimin Niu Nianxiong Tan Xiaopeng Yu 0002 Hongzhong Zheng Jianyi Meng Xiaolang Yan Yuan Xie 0001 Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. 483-490 2022 ICPADS https://doi.org/10.1109/ICPADS56603.2022.00069 conf/icpads/2022 db/conf/icpads/icpads2022.html#DuGGNTYZMYX22

Zhaoyang Du Yijin Guan Tianchan Guan Dimin Niu Nianxiong Tan Xiaopeng Yu 0002 Hongzhong Zheng Jianyi Meng Xiaolang Yan Yuan Xie 0001 Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. 2022 abs/2207.13848 CoRR https://doi.org/10.48550/arXiv.2207.13848 db/journals/corr/corr2207.html#abs-2207-13848

Chen Chen 0058 Xiaoyan Xiang Chang Liu 0021 Yunhai Shang Ren Guo Dongqi Liu 0003 Yimin Lu Ziyi Hao Jiahui Luo Zhijian Chen Chunqiang Li Yu Pu Jianyi Meng Xiaolang Yan Yuan Xie 0001 Xiaoning Qi Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. 1-19 2020 Hot Chips Symposium https://doi.org/10.1109/HCS49909.2020.9220630 conf/hotchips/2020 db/conf/hotchips/hotchips2020.html#0058XLSGLLHLCLP20 Chen Chen 0058 Xiaoyan Xiang Chang Liu 0021 Yunhai Shang Ren Guo Dongqi Liu 0003 Yimin Lu Ziyi Hao Jiahui Luo Zhijian Chen Chunqiang Li Yu Pu Jianyi Meng Xiaolang Yan Yuan Xie 0001 Xiaoning Qi Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. 52-64 2020 ISCA https://doi.org/10.1109/ISCA45697.2020.00016 conf/isca/2020 db/conf/isca/isca2020.html#ChenXLSGLLHLCLP20

Huibin Wang Chunqiang Li Jianyi Meng Xiaoyan Xiang SCSE: Boosting Symbolic Execution via State Concretization. 1506-1516 2019 102-D IEICE Trans. Inf. Syst. 8 https://doi.org/10.1587/transinf.2018EDP7298 http://search.ieice.org/bin/summary.php?id=e102-d_8_1506 db/journals/ieicet/ieicet102d.html#WangLMX19

Yin Xu 0003 Zhijian Chen Feiteng Li Jianyi Meng A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification. 2172-2176 2019 38 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2018.2871819 db/journals/tcad/tcad38.html#XuCLM19

Zhijian Chen Menghan Jia Jiahui Luo Tao-Tao Zhu Xiaoyan Xiang Jianyi Meng A low power QRS detection processor with adaptive scaling of processing resolution. 20170882 2018 15 IEICE Electron. Express 1 https://doi.org/10.1587/elex.14.20170882 db/journals/ieiceee/ieiceee15.html#ChenJLZXM18

Yan He Jianyi Meng Zhijian Chen Xiaoyan Xiang Chen Chen 0058 An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. 20171229 2018 15 IEICE Electron. Express 3 https://doi.org/10.1587/elex.15.20171229 db/journals/ieiceee/ieiceee15.html#HeMCXC18

Yin Xu 0003 Zhijian Chen Xiaoyan Xiang Jianyi Meng An energy-efficient parallel VLSI architecture for SVM classification. 20180099 2018 15 IEICE Electron. Express 7 https://doi.org/10.1587/elex.15.20180099 db/journals/ieiceee/ieiceee15.html#XuCXM18

Jiahui Luo Zhijian Chen Xiaoyan Xiang Jianyi Meng A Highly Adaptive Lossless ECG Compression ASIC for Wireless Sensors Based on Hybrid Gomlomb Coding. 791-794 2018 101-D IEICE Trans. Inf. Syst. 3 https://doi.org/10.1587/transinf.2017EDL8206 http://search.ieice.org/bin/summary.php?id=e101-d_3_791 db/journals/ieicet/ieicet101d.html#LuoCXM18

Yande Xiang Jiahui Luo Tao-Tao Zhu Sheng Wang 0005 Xiaoyan Xiang Jianyi Meng ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. 1189-1198 2018 101-D IEICE Trans. Inf. Syst. 4 https://doi.org/10.1587/transinf.2017EDP7285 http://search.ieice.org/bin/summary.php?id=e101-d_4_1189 db/journals/ieicet/ieicet101d.html#XiangLZWXM18

Zhitao Lin De Ma Jianyi Meng Linna Chen Relative ordering learning in spiking neural network for pattern recognition. 94-106 2018 275 Neurocomputing https://doi.org/10.1016/j.neucom.2017.05.009 db/journals/ijon/ijon275.html#LinMMC18

Zhijian Chen Huanzhang Xu Jiahui Luo Tao-Tao Zhu Jianyi Meng Low-power perceptron model based ECG processor for premature ventricular contraction detection. 29-36 2018 59 Microprocess. Microsystems https://doi.org/10.1016/j.micpro.2018.03.006 https://www.wikidata.org/entity/Q130096873 db/journals/mam/mam59.html#ChenXLZM18

Yande Xiang Jianyi Meng A Cross-layer based mapping for spiking neural network onto network on chip. 526-544 2018 33 Int. J. Parallel Emergent Distributed Syst. 5 https://doi.org/10.1080/17445760.2017.1399206 db/journals/paapp/paapp33.html#XiangM18

Zhijian Chen Jiahui Luo Kaiwen Lin Jiaquan Wu Tao-Tao Zhu Xiaoyan Xiang Jianyi Meng An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. 948-952 2018 65-II IEEE Trans. Circuits Syst. II Express Briefs 7 https://doi.org/10.1109/TCSII.2017.2747596 db/journals/tcas/tcasII65.html#ChenLLWZXM18

Tao-Tao Zhu Xiaoyan Xiang Chen Chen 0058 Jianyi Meng SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. 20170218 2017 14 IEICE Electron. Express 8 https://doi.org/10.1587/elex.14.20170218 db/journals/ieiceee/ieiceee14.html#ZhuXCM17

Sheng Wang 0005 Chen Chen 0058 Xiaoyan Xiang Jianyi Meng A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. 20170353 2017 14 IEICE Electron. Express 11 https://doi.org/10.1587/elex.14.20170353 db/journals/ieiceee/ieiceee14.html#WangCXM17

Jiahui Luo Zhijian Chen Xiaoyan Xiang Jianyi Meng Haibin Shen A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression. 20170524 2017 14 IEICE Electron. Express 12 https://doi.org/10.1587/elex.14.20170524 db/journals/ieiceee/ieiceee14.html#LuoCXMS17

Jiahui Luo Zhijian Chen Xiaoyan Xiang Jianyi Meng A lifting wavelet based lossless and lossy ECG compression processor for wireless sensors. 20170865 2017 14 IEICE Electron. Express 20 https://doi.org/10.1587/elex.14.20170865 db/journals/ieiceee/ieiceee14.html#LuoCXM17

Yin Xu 0003 Zhijian Chen Xiaoyan Xiang Jianyi Meng A granular resampling method based energy-efficient architecture for heartbeat classification in ECG. 20170984 2017 14 IEICE Electron. Express 22 https://doi.org/10.1587/elex.14.20170984 db/journals/ieiceee/ieiceee14.html#XuCXM17

Zhan-Hui Li Tao-Tao Zhu Zhi-Jian Chen Jian-Yi Meng Xiaoyan Xiang Xiaolang Yan Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. 670-682 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/TVLSI.2016.2587810 db/journals/tvlsi/tvlsi25.html#LiZCMXY17

Tao-Tao Zhu Jian-Yi Meng Xiaoyan Xiang Xiaolang Yan Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. 1681-1693 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2017.2652482 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2652482 db/journals/tvlsi/tvlsi25.html#ZhuMXY17

Sheng Wang 0005 Chen Chen 0058 Xiaoyan Xiang Jian-Yi Meng A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. 1993-2006 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2017.2676026 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2676026 db/journals/tvlsi/tvlsi25.html#WangCXM17

Zhenqiang Yong Xiaoyan Xiang Chen Chen 0058 Jianyi Meng An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. 3534-3538 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2017.2748228 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2748228 db/journals/tvlsi/tvlsi25.html#YongXCM17

Zhenqiang Yong Xiaoyan Xiang Chen Chen 0058 Jianyi Meng A new error masking flip-flop with one cycle correction penalty. 72-75 2017 ASICON https://doi.org/10.1109/ASICON.2017.8252414 conf/asicon/2017 db/conf/asicon/asicon2017.html#YongXCM17 Xiaopei Chen Sheng Wang 0005 Xiaoyan Xiang Chen Chen 0058 Jianyi Meng A light-weight energy-efficient resilient circuit for variation tolerance. 815-818 2017 ASICON https://doi.org/10.1109/ASICON.2017.8252601 conf/asicon/2017 db/conf/asicon/asicon2017.html#ChenWXCM17

Chaojun Zhao Chen Chen 0058 Zhijian Chen Jianyi Meng Value locality based storage compression memory architecture for ECG sensor node. 042401:1-042401:11 2016 59 Sci. China Inf. Sci. 4 https://doi.org/10.1007/s11432-015-5371-1 db/journals/chinaf/chinaf59.html#ZhaoCCM16

Jing Qiu Xiaoyan Xiang Zhijian Chen Jianyi Meng Yong Ding 0003 Ultralow power processor employing block instruction for ECG applications. 20150493 2016 13 IEICE Electron. Express 2 https://doi.org/10.1587/elex.13.20150493 db/journals/ieiceee/ieiceee13.html#QiuXCMD16

Li Zhanhui Yong Ding 0003 Xiaolang Yan Jianyi Meng Xiaoyan Xiang Light-weight one-cycle timing error correction based on hardware software co-design. 20160411 2016 13 IEICE Electron. Express 11 https://doi.org/10.1587/elex.13.20160411 db/journals/ieiceee/ieiceee13.html#ZhanhuiDYMX16

Ziyi Hao Xiaoyan Xiang Chen Chen 0058 Jianyi Meng Yong Ding 0003 Xiaolang Yan EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. 20160682 2016 13 IEICE Electron. Express 16 https://doi.org/10.1587/elex.13.20160682 db/journals/ieiceee/ieiceee13.html#HaoXCMDY16

Zhenqiang Yong Xiaoyan Xiang Jianyi Meng Chen Chen 0058 TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. 20160766 2016 13 IEICE Electron. Express 20 https://doi.org/10.1587/elex.13.20160766 db/journals/ieiceee/ieiceee13.html#YongXMC16

Ziyi Hao Xiaoyan Xiang Chen Chen 0058 Jianyi Meng A timing failure tolerance design with in-field simultaneous error detection and correction. 1-4 2015 ASICON https://doi.org/10.1109/ASICON.2015.7517164 conf/asicon/2015 db/conf/asicon/asicon2015.html#HaoXCM15 Sheng Wang 0005 Xiaoyan Xiang Chen Chen 0058 Jianyi Meng An energy-efficient microprocessor using multilevel error correction for timing error tolerance. 1-4 2015 ASICON https://doi.org/10.1109/ASICON.2015.7517180 conf/asicon/2015 db/conf/asicon/asicon2015.html#WangXCM15 Tao-Tao Zhu Xiaoyan Xiang Chen Chen 0058 Jianyi Meng A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. 1-4 2015 ASICON https://doi.org/10.1109/ASICON.2015.7517178 conf/asicon/2015 db/conf/asicon/asicon2015.html#ZhuXCM15

Sheng-Kai Yang Jian-Yi Meng Haibin Shen Preservation of local linearity by neighborhood subspace scaling for solving the pre-image problem. 254-264 2014 15 J. Zhejiang Univ. Sci. C 4 https://doi.org/10.1631/jzus.C1300248 db/journals/jzusc/jzusc15.html#YangMS14

Chen Chen 0058 Linna Chen Xiaopei Chen Zhi-Jian Chen Zhijian Chen Yong Ding 0003 Zhaoyang Du Tianchan Guan Yijin Guan Ren Guo Jun Han 0003 Ziyi Hao Yan He Menghan Jia Honglin Kuang Chunqiang Li Feiteng Li Zhan-Hui Li Kaiwen Lin Zhitao Lin Chang Liu 0021 Dongqi Liu 0003 Yimin Lu Jiahui Luo De Ma Dimin Niu Yu Pu Xiaoning Qi Jing Qiu Yunhai Shang Haibin Shen Yi Sun Nianxiong Tan Huibin Wang Sheng Wang 0005 Jiaquan Wu Xiaoyan Xiang Yande Xiang Yuan Xie 0001 Huanzhang Xu Yin Xu 0003 Xiaolang Yan Sheng-Kai Yang Zhen Yang Zhenqiang Yong Xiaopeng Yu 0002 Xinglong Yu Li Zhanhui Chaojun Zhao Yifan Zhao 0007 Hongzhong Zheng Tao-Tao Zhu