A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Mohammad Daud

Anuj Grover G. S. Visweswaran Chittoor R. Parthasarathy Mohammad Daud David Turgis Bastien Giraud Jean-Philippe Noel Ivan Miro Panades Guillaume Moritz Edith Beigné Philippe Flatresse Promod Kumar Shamsi Azmi A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. 2438-2447 2017 64-I IEEE Trans. Circuits Syst. I Regul. Pap. 9 https://doi.org/10.1109/TCSI.2017.2705116 db/journals/tcas/tcasI64.html#GroverVPDTGNPMB17

Anuj Grover Promod Kumar Mohammad Daud G. S. Visweswaran Chittoor R. Parthasarathy Jean-Philippe Noel David Turgis Bastien Giraud Guillaume Moritz Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. 1-4 2015 ICICDT https://doi.org/10.1109/ICICDT.2015.7165876 conf/icicdt/2015 db/conf/icicdt/icicdt2015.html#GroverKDVPNTGM15 Shamsi Azmi Edith Beigné Philippe Flatresse Bastien Giraud Anuj Grover Promod Kumar Guillaume Moritz Jean-Philippe NoëlJean-Philippe Noel Ivan Miro Panades Chittoor R. Parthasarathy David Turgis G. S. Visweswaran