Dynamic partially reconfigurable architecture for fast Fourier transform computation.

Jih-Sheng Shen

Hung-Lin Chao Cheng-Chien Wu Chun-Yang Peng Chun-Hsien Lu Jih-Sheng Shen Pao-Ann Hsiung Dynamic partially reconfigurable architecture for fast Fourier transform computation. 207-215 2014 6 Int. J. Embed. Syst. 2/3 https://doi.org/10.1504/IJES.2014.063818 db/journals/ijes/ijes6.html#ChaoWPLSH14

Jih-Sheng Shen Pao-Ann Hsiung Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip. 1777-1790 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2013.2278334 db/journals/tvlsi/tvlsi22.html#ShenH14

Jih-Sheng Shen Pao-Ann Hsiung Juin-Ming Lu Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. 523-526 2014 HPCS https://doi.org/10.1109/HPCSim.2014.6903730 conf/hpcs/2014 db/conf/hpcs/hpcs2014.html#ShenHL14

Jih-Sheng Shen Pao-Ann Hsiung Chun-Hsian Huang Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption. 453-464 2013 39 Comput. Electr. Eng. 2 https://doi.org/10.1016/j.compeleceng.2012.09.013 db/journals/cee/cee39.html#ShenHH13

Hung-Lin Chao Chun-Yang Peng Cheng-Chien Wu Ken-Shin Huang Chun-Hsien Lu Jih-Sheng Shen Pao-Ann Hsiung Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design. 426-429 2013 FPT https://doi.org/10.1109/FPT.2013.6718405 conf/fpt/2013 db/conf/fpt/fpt2013.html#ChaoPWHLSH13 Wan-Ting Su Jih-Sheng Shen Pao-Ann Hsiung Network-on-Chip router design with Buffer-Stealing. 160-164 2011 ASP-DAC https://doi.org/10.1109/ASPDAC.2011.5722177 http://dl.acm.org/citation.cfm?id=1950859 conf/aspdac/2011 db/conf/aspdac/aspdac2011.html#SuSH11 Jih-Sheng Shen Pao-Ann Hsiung Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication. I-XVII, 1-366 IGI Global 2010 978-1-61520-807-4 https://doi.org/10.4018/978-1-61520-807-4

Chun-Hsian Huang Pao-Ann Hsiung Jih-Sheng Shen UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems. 88-102 2010 56 J. Syst. Archit. 2-3 https://doi.org/10.1016/j.sysarc.2009.11.007 https://www.wikidata.org/entity/Q113441095 db/journals/jsa/jsa56.html#HuangHS10

Chun-Hsian Huang Pao-Ann Hsiung Jih-Sheng Shen Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption. 545-560 2010 56 J. Syst. Archit. 11 https://doi.org/10.1016/j.sysarc.2010.07.007 db/journals/jsa/jsa56.html#HuangHS10a

Pao-Ann Hsiung Chun-Hsian Huang Jih-Sheng Shen Cheng-Chi Chiang Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems. 9:1-9:32 2010 4 ACM Trans. Reconfigurable Technol. Syst. 1 https://doi.org/10.1145/1857927.1857936 https://www.wikidata.org/entity/Q130971909 db/journals/trets/trets4.html#HsiungHSC10

Jih-Sheng Shen Chun-Hsian Huang Pao-Ann Hsiung Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. 381-386 2010 DATE https://doi.org/10.1109/DATE.2010.5457173 http://dl.acm.org/citation.cfm?id=1871019 conf/date/2010 db/conf/date/date2010.html#ShenHH10 Chun-Hsian Huang Jih-Sheng Shen Pao-Ann Hsiung A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications. 382-396 2010 UIC https://doi.org/10.1007/978-3-642-16355-5_31 conf/uic/2010 db/conf/uic/uic2010.html#HuangSH10

Kuei-Chung Chang Jih-Sheng Shen Tien-Fu Chen Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. 2008 13 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/1297666.1297678 db/journals/todaes/todaes13.html#ChangSC08 12:1-12:31

Jih-Sheng Shen Pao-Ann Hsiung Kuei-Chung Chang A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability. 1-8 2008 ACSAC https://doi.org/10.1109/APCSAC.2008.4625439 https://doi.ieeecomputersociety.org/10.1109/APCSAC.2008.4625439 conf/aPcsac/2008 db/conf/aPcsac/aPcsac2008.html#ShenHC08 Kuei-Chung Chang Jih-Sheng Shen Tien-Fu Chen Fast Run-Time Power Monitoring Methodology for Embedded Systems. 129-133 2006 conf/csreaESA/2006 ESA db/conf/csreaESA/csreaESA2006.html#ChangSC06 Kuei-Chung Chang Jih-Sheng Shen Tien-Fu Chen Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. 143-148 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1146950 db/conf/dac/dac2006.html#ChangSC06 Jih-Sheng Shen Kuei-Chung Chang Tien-Fu Chen On a design of crossroad switches for low-power on-chip communication architectures. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692626 db/conf/iscas/iscas2006.html#ShenCC06 Kuei-Chung Chang Jih-Sheng Shen Tien-Fu Chen Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. 151-157 2005 conf/csreaESA/2005 ESA db/conf/csreaESA/csreaESA2005.html#ChangSC05 Kuei-Chung Chang Jih-Sheng Shen Tien-Fu Chen A low-power crossroad switch architecture and its core placement for network-on-chip. 375-380 2005 conf/islped/2005 ISLPED https://doi.org/10.1145/1077603.1077693 db/conf/islped/islped2005.html#ChangSC05 Kuei-Chung Chang Hung-Lin Chao Tien-Fu Chen Cheng-Chi Chiang Pao-Ann Hsiung Chun-Hsian Huang Ken-Shin Huang Chun-Hsien Lu Juin-Ming Lu Chun-Yang Peng Wan-Ting Su Cheng-Chien Wu