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Shanthi Pavan

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with coauthor community group 5

> Home > Persons > Shanthi Pavan

Publications

2025
[j79]
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Chaitanya Kumar, Shanthi Pavan:
Weak Nonlinearities in Active Filters and Continuous-Time Pipeline ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 72(12): 7565-7577 (2025)
2024
[j77]
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Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj:
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining. IEEE J. Solid State Circuits 59(1): 268-281 (2024)
2023
[j73]
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Chaitanya Kumar, Shanthi Pavan:
Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3832-3842 (2023)
[j72]
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Nishanth Basavaraj, Shanthi Pavan:
Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5086-5097 (2023)
2022
[j70]
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Shanthi Pavan, Saravana Manivannan:
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 530-540 (2022)
[j69]
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Saravana Manivannan, Shanthi Pavan:
Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3102-3113 (2022)
[j66]
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Nishanth Basavaraj, Saravana Manivannan, Shanthi Pavan:
Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3993-3997 (2022)
[c56]
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Chaitanya Kumar, Saravana Manivannan, Shanthi Pavan:
Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC. ISCAS 2022: 2792-2796
2020
[j60]
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Saravana Manivannan, Shanthi Pavan:
Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering. IEEE Trans. Circuits Syst. 67-I(11): 3778-3789 (2020)
2019
[c50]
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Saravana Manivannan, Shanthi Pavan:
Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities. ISCAS 2019: 1-5
2018
[j51]
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Saravana Manivannan, Shanthi Pavan:
Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3207-3215 (2018)
[c47]
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Saravana Manivannan, Shanthi Pavan:
A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR. CICC 2018: 1-4

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