A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.

John Poulton John W. Poulton NVIDIA Inc., Durham, NC, USA PhD University of North Carolina, Chapel Hill, NC, USA https://research.nvidia.com/person/john-poulton https://en.wikipedia.org/wiki/John_Poulton https://www.wikidata.org/entity/Q29472834

Yoshinori Nishi John W. Poulton Walker J. Turner Xi Chen 0033 Sanquan Song Brian Zimmer Stephen G. Tell Nikola Nedovic John M. Wilson 0002 William J. Dally C. Thomas Gray A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. 1146-1157 2024 April 59 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2023.3338478 db/journals/jssc/jssc59.html#NishiPTCSZTNWDG24

Walker J. Turner John W. Poulton Yoshinori Nishi Xi Chen 0033 Brian Zimmer Sanquan Song John M. Wilson 0002 William J. Dally C. Thomas Gray Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. 1-7 2024 CICC https://doi.org/10.1109/CICC60959.2024.10529010 conf/cicc/2024 db/conf/cicc/cicc2024.html#TurnerPNCZSWDG24

Yoshinori Nishi John W. Poulton Walker J. Turner Xi Chen 0033 Sanquan Song Brian Zimmer Stephen G. Tell Nikola Nedovic John M. Wilson 0002 William J. Dally C. Thomas Gray A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. 1062-1073 2023 58 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2022.3232024 db/journals/jssc/jssc58.html#NishiPTCSZTNWDG23

Yoshinori Nishi John W. Poulton Xi Chen 0033 Sanquan Song Brian Zimmer Walker J. Turner Stephen G. Tell Nikola Nedovic John M. Wilson 0002 William J. Dally C. Thomas Gray A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. 1-2 2023 VLSI Technology and Circuits https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185334 conf/vlsit/2023 db/conf/vlsit/vlsit2023.html#NishiPCSZTTN0DG23 Yoshinori Nishi John W. Poulton Xi Chen 0033 Sanquan Song Brian Zimmer Walker J. Turner Stephen G. Tell Nikola Nedovic John M. Wilson 0002 William J. Dally C. Thomas Gray A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. 154-155 2022 VLSI Technology and Circuits https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830174 conf/vlsit/2022 db/conf/vlsit/vlsit2022.html#NishiPCSZTTN0DG22 Xi Chen 0033 Nikola Nedovic Stephen G. Tell Sudhir S. Kudva Brian Zimmer Thomas H. Greer John W. Poulton Sanquan Song Walker J. Turner John M. Wilson 0002 C. Thomas Gray 6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. 126-128 2020 ISSCC https://doi.org/10.1109/ISSCC19947.2020.9063140 conf/isscc/2020 db/conf/isscc/isscc2020.html#0033NTKZGPST0G20

John W. Poulton John M. Wilson 0002 Walker J. Turner Brian Zimmer Xi Chen 0033 Sudhir S. Kudva Sanquan Song Stephen G. Tell Nikola Nedovic Wenxu Zhao Sunil R. Sudhakaran C. Thomas Gray William J. Dally A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. 43-54 2019 54 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2018.2875092 https://www.wikidata.org/entity/Q128960839 db/journals/jssc/jssc54.html#PoultonWTZCKSTN19

Xi Chen 0033 Sanquan Song John Poulton Nikola Nedovic Brian Zimmer Stephen G. Tell C. Thomas Gray Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. 1-4 2019 CICC https://doi.org/10.1109/CICC.2019.8780309 conf/cicc/2019 db/conf/cicc/cicc2019.html#0033SPNZTG19 Sanquan Song John Poulton Xi Chen 0033 Brian Zimmer Stephen G. Tell Walker J. Turner Sudhir S. Kudva Nikola Nedovic John M. Wilson 0002 C. Thomas Gray William J. Dally A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. 1-4 2019 CICC https://doi.org/10.1109/CICC.2019.8780177 conf/cicc/2019 db/conf/cicc/cicc2019.html#SongP0ZTTKNWGD19 Sudhir S. Kudva Sanquan Song John W. Poulton John M. Wilson 0002 Wenxu Zhao C. Thomas Gray A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. 1-4 2018 CICC https://doi.org/10.1109/CICC.2018.8357021 conf/cicc/2018 db/conf/cicc/cicc2018.html#KudvaSP0ZG18 Walker J. Turner John W. Poulton John M. Wilson 0002 Xi Chen 0033 Stephen G. Tell Matthew Fojtik Thomas H. Greer Brian Zimmer Sanquan Song Nikola Nedovic Sudhir S. Kudva Sunil R. Sudhakaran Rizwan Bashirullah Wenxu Zhao William J. Dally C. Thomas Gray Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. 1-8 2018 CICC https://doi.org/10.1109/CICC.2018.8357077 conf/cicc/2018 db/conf/cicc/cicc2018.html#TurnerP0CTFGZSN18 John M. Wilson 0002 Walker J. Turner John W. Poulton Brian Zimmer Xi Chen 0033 Sudhir S. Kudva Sanquan Song Stephen G. Tell Nikola Nedovic Wenxu Zhao Sunil R. Sudhakaran C. Thomas Gray William J. Dally A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. 276-278 2018 ISSCC https://doi.org/10.1109/ISSCC.2018.8310291 conf/isscc/2018 db/conf/isscc/isscc2018.html#0002TPZCKSTNZSG18 William J. Dally C. Thomas Gray John Poulton Brucek Khailany John M. Wilson 0002 Larry R. Dennison Hardware-Enabled Artificial Intelligence. 3-6 2018 VLSI Circuits https://doi.org/10.1109/VLSIC.2018.8502368 conf/vlsic/2018 db/conf/vlsic/vlsic2018.html#DallyGPK0D18 Arijit Banerjee 0002 Ningxi Liu Harsh N. Patel Benton H. Calhoun John W. Poulton C. Thomas Gray A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. 1-4 2017 CICC https://doi.org/10.1109/CICC.2017.7993688 conf/cicc/2017 db/conf/cicc/cicc2017.html#BanerjeeLPCPG17 Laura Fick Dennis Sylvester John W. Poulton John M. Wilson 0002 C. Thomas Gray A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050445 conf/iscas/2017 db/conf/iscas/iscas2017.html#FickSPWG17

Mahmut E. Sinangil John W. Poulton Matthew R. Fojtik Thomas H. Greer Stephen G. Tell Andreas J. Gotterba Jesse Wang Jason Golbus Brian Zimmer William J. Dally C. Thomas Gray A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. 557-567 2016 51 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/JSSC.2015.2498302 db/journals/jssc/jssc51.html#SinangilPFGTGWG16

John M. Wilson 0002 Matthew R. Fojtik John W. Poulton Xi Chen 0033 Stephen G. Tell Thomas H. Greer C. Thomas Gray William J. Dally 8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. 156-157 2016 ISSCC https://doi.org/10.1109/ISSCC.2016.7417954 conf/isscc/2016 db/conf/isscc/isscc2016.html#WilsonFPCTGGD16 Arijit Banerjee 0002 Mahmut E. Sinangil John W. Poulton C. Thomas Gray Benton H. Calhoun A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. 1-8 2014 ISQED https://doi.org/10.1109/ISQED.2014.6783299 conf/isqed/2014 db/conf/isqed/isqed2014.html#BanerjeeSPGC14

John W. Poulton William J. Dally Xi Chen 0033 John G. Eyles Thomas H. Greer Stephen G. Tell John M. Wilson 0002 C. Thomas Gray A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. 3206-3218 2013 48 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2013.2279053 db/journals/jssc/jssc48.html#PoultonDCEGTWG13

John W. Poulton William J. Dally Xi Chen 0033 John G. Eyles Thomas H. Greer Stephen G. Tell C. Thomas Gray A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. 404-405 2013 ISSCC https://doi.org/10.1109/ISSCC.2013.6487789 conf/isscc/2013 db/conf/isscc/isscc2013.html#PoultonDCEGTG13

Brian S. Leibowitz Robert Palmer John Poulton Yohan Frans Simon Li John M. Wilson 0002 Michael Bucher Andrew M. Fuller John G. Eyles Marko Aleksic Trey Greer Nhat Nguyen A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. 889-898 2010 45 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2010.2040230 db/journals/jssc/jssc45.html#LeibowitzPPFLWBFEAGN10

John Poulton Robert Palmer Andrew M. Fuller Trey Greer John G. Eyles William J. Dally Mark Horowitz A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. 2745-2757 2007 42 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2007.908692 db/journals/jssc/jssc42.html#PoultonPFGEDH07

Robert Palmer John Poulton William J. Dally John G. Eyles Andrew M. Fuller Trey Greer Mark Horowitz Mark Kellam F. Quan F. Zarkeshvari A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. 440-614 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373483 conf/isscc/2007 db/conf/isscc/isscc2007.html#PalmerPDEFGHKQZ07

Mike Yun He John Poulton A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. 597-606 2006 41 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/JSSC.2006.869792 db/journals/jssc/jssc41.html#HeP06

Ramin Farjad-Rad Anhtuyet Nguyen James Tran Trey Greer John Poulton William J. Dally John H. Edmondson Ramesh Senthinathan Rohit Rathi Ming-Ju Edward Lee Hiok-Tiaq Ng A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. 1553-1561 2004 39 IEEE J. Solid State Circuits 9 https://doi.org/10.1109/JSSC.2004.831457 db/journals/jssc/jssc39.html#Farjad-RadNTGPD04

Chris Dwyer Leandra Vicci John W. Poulton Dorothy Erie Richard Superfine Sean Washburn Russell M. Taylor II The design of DNA self-assembled computing circuitry. 1214-1220 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2004.836322 db/journals/tvlsi/tvlsi12.html#DwyerVPESWT04

Ming-Ju Edward Lee William J. Dally Trey Greer Hiok-Tiaq Ng Ramin Farjad-Rad John Poulton Ramesh Senthinathan Jitter transfer characteristics of delay-locked loops - theories and design techniques. 614-621 2003 38 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2003.809519 db/journals/jssc/jssc38.html#LeeDGNFPS03

Hiok-Tiaq Ng Ramin Farjad-Rad Ming-Ju Edward Lee William J. Dally Trey Greer John Poulton John H. Edmondson Rohit Rathi Ramesh Senthinathan A second-order semidigital clock recovery circuit based on injection locking. 2101-2110 2003 38 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2003.818576 db/journals/jssc/jssc38.html#NgFLDGPERS03

Hiok-Tiaq Ng Ming-Ju Edward Lee Ramin Farjad-Rad Ramesh Senthinathan William J. Dally Anhtuyet Nguyen Rohit Rathi Trey Greer John Poulton John H. Edmondson James Tran A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. 77-80 2003 CICC https://doi.org/10.1109/CICC.2003.1249363 conf/cicc/2003 db/conf/cicc/cicc2003.html#NgLFSDNRGPET03 Ming-Ju Edward Lee William J. Dally Ramin Farjad-Rad Hiok-Tiaq Ng Ramesh Senthinathan John H. Edmondson John W. Poulton CMOS High-Speed I/Os - Present and Future. 454-461 2003 conf/iccd/2003 ICCD https://doi.org/10.1109/ICCD.2003.1240940 https://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240940 db/conf/iccd/iccd2003.html#LeeDFNSEP03

Ramin Farjad-Rad William J. Dally Hiok-Tiaq Ng Ramesh Senthinathan Ming-Ju Edward Lee Rohit Rathi John Poulton A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. 1804-1812 2002 37 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2002.804340 db/journals/jssc/jssc37.html#Farjad-RadDNSLR02

William J. Dally John W. Poulton Digital systems engineering. I-XXIV, 1-663 Cambridge University Press 2001 978-0-521-59292-5 John Poulton Problems and Prospects for Electrical Signaling. 326- 1999 conf/arvlsi/1999 ARVLSI https://doi.org/10.1109/ARVLSI.1999.833402 https://doi.ieeecomputersociety.org/10.1109/ARVLSI.1999.833402 db/conf/arvlsi/arvlsi1999.html#Poulton99

John Poulton William J. Dally Steve Tell A tracking clock recovery receiver for 4-Gbps signaling. 25-27 1998 18 IEEE Micro 1 https://doi.org/10.1109/40.653023 http://doi.ieeecomputersociety.org/10.1109/40.653023 db/journals/micro/micro18.html#PoultonDT98

William J. Dally John W. Poulton Transmitter equalization for 4-Gbps signaling. 48-56 1997 17 IEEE Micro 1 https://doi.org/10.1109/40.566199 http://doi.ieeecomputersociety.org/10.1109/40.566199 db/journals/micro/micro17.html#DallyP97

John Poulton An Embedded DRAM for CMOS ASICs. 288-302 1997 conf/arvlsi/1997 ARVLSI https://doi.org/10.1109/ARVLSI.1997.634861 https://doi.ieeecomputersociety.org/10.1109/ARVLSI.1997.634861 db/conf/arvlsi/arvlsi1997.html#Poulton97 John G. Eyles Steven Molnar John Poulton Trey Greer Anselmo Lastra Nick England Lee Westover PixelFlow: The Realization. 57-67 1997 Workshop on Graphics Hardware https://doi.org/10.2312/EGGH/EGGH97/057-067 https://doi.org/10.1145/258694.258714 conf/egh/1997 db/conf/egh/egh1997.html#EylesMPGLEW97

John Poulton John G. Eyles Steven E. Molnar Henry Fuchs Breaking the frame-buffer bottleneck with logic-enhanced memories. 65-74 1992 12 IEEE Computer Graphics and Applications 6 https://doi.org/10.1109/38.163626 http://doi.ieeecomputersociety.org/10.1109/38.163626 db/journals/cga/cga12.html#PoultonEMF92

Steven Molnar John G. Eyles John Poulton PixelFlow: high-speed rendering using image composition. 231-240 1992 conf/siggraph/1992 SIGGRAPH https://doi.org/10.1145/133994.134067 db/conf/siggraph/siggraph1992.html#MolnarEP92 Henry Fuchs John Poulton John G. Eyles Trey Greer Jack Goldfeather David A. Ellsworth Steven Molnar Greg Turk Brice Tebbs Laura Israel Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. 79-88 1989 conf/siggraph/1989 SIGGRAPH https://doi.org/10.1145/74333.74341 db/conf/siggraph/siggraph1989.html#FuchsPEGGEMTTI89 John G. Eyles John D. Austin Henry Fuchs Trey Greer John Poulton Pixel-Planes 4: A Summary. 183-207 1987 conf/egh/1987 Advances in Computer Graphics Hardware db/conf/egh/egh1987.html#EylesAFGP87 https://doi.org/10.2312/EGGH/EGGH87/183-207 Henry Fuchs Jack Goldfeather Jeff P. Hultquist Susan Spach John D. Austin Frederick P. Brooks Jr. John G. Eyles John Poulton Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes. 169-187 1985 conf/egt/1985 Advances in Computer Graphics db/conf/egt/egt1985.html#FuchsGHSABEP85 Henry Fuchs Jack Goldfeather Jeff P. Hultquist Susan Spach John D. Austin Frederick P. Brooks Jr. John G. Eyles John Poulton Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes. 111-120 1985 conf/siggraph/1985 SIGGRAPH https://doi.org/10.1145/325334.325205 db/conf/siggraph/siggraph1985.html#FuchsGHSABEP85 Jonathan B. Rosenberg David G. Boyer John A. Dallen Stephen W. Daniel Charles J. Poirier John Poulton C. Durward Rogers Neil Weste A vertically integrated VLSI design environment. 31-38 1983 DAC http://dl.acm.org/citation.cfm?id=800637 conf/dac/1983 db/conf/dac/dac1983.html#RosenbergBDDPPRW83 Marko Aleksic John D. Austin Arijit Banerjee 0002 Rizwan Bashirullah David G. Boyer Frederick P. Brooks Jr. Michael Bucher Benton H. Calhoun Xi Chen 0033 John A. Dallen William J. Dally Stephen W. Daniel Larry DennisonLarry R. Dennison Chris Dwyer John H. Edmondson David A. Ellsworth Nick England Dorothy Erie John G. Eyles Ramin Farjad-Rad Laura Fick Matthew FojtikMatthew R. Fojtik Yohan Frans Henry Fuchs Andrew M. Fuller Jason Golbus Jack Goldfeather Andreas J. Gotterba C. Thomas Gray Thomas H. Greer Trey Greer Mike Yun He Mark Horowitz Jeff P. Hultquist Laura Israel Mark Kellam Brucek Khailany Sudhir S. Kudva Anselmo Lastra Ming-Ju Edward Lee Brian S. Leibowitz Simon Li Ningxi Liu Steven E. MolnarSteven Molnar Nikola Nedovic Hiok-Tiaq Ng Anhtuyet Nguyen Nhat Nguyen Yoshinori Nishi Robert Palmer Harsh N. Patel Charles J. Poirier F. Quan Rohit Rathi C. Durward Rogers Jonathan B. Rosenberg Ramesh Senthinathan Mahmut E. Sinangil Sanquan Song Susan Spach Sunil R. Sudhakaran Richard Superfine Dennis Sylvester Russell M. Taylor II Brice Tebbs Stephen G. Tell Steve Tell Jimmy TranJames Tran Greg Turk Walker J. Turner Leandra Vicci Jesse Wang Sean Washburn Neil Weste Lee Westover John M. Wilson 0002 F. Zarkeshvari Wenxu Zhao Brian Zimmer