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BibTeX records: Vinson Chan
@inproceedings{DBLP:conf/cicc/VenkataCTLNKNZX05,
author = {Ramanand Venkata and
Vinson Chan and
Binh Ton and
Chong Lee and
Huy Ngo and
Malik Kabani and
Tam Nguyen and
Arch Zaliznyak and
Ning Xue and
Steven Shen and
Michael Zheng and
Michael Lai and
Steve Park and
Lana Chan and
Divya Vijayaraghavan and
John Lam and
Rakesh H. Patel},
title = {Multi-protocol embedded {PCS} {IP} in a {FPGA-SOC}},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {783--786},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568785},
doi = {10.1109/CICC.2005.1568785},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/VenkataCTLNKNZX05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/VenkataWTCHLTSL03,
author = {Ranianand Venkata and
Wilson Wong and
Tina Tran and
Vinson Chan and
Tim Hoang and
Henry Lui and
Uinh Ton and
Sergey Shomurryev and
Chong Lee and
Shoujun Waiig and
Huy Ngo and
Malik Kdhani and
Victor Maruri and
Tin Lai and
Tam Kpuyeu and
Arch Zaliziiyak and
Mei Luo and
Toan Nguyen and
Kazi Asaduzzaman and
Siniardeep Maangat and
John Lam and
Rakesh Patel},
title = {Architecture and methodology of a SoPC with 3.25Gbps {CDR} based {SERDES}
and 1Gbps dynamic phase alignment},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {659--662},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249481},
doi = {10.1109/CICC.2003.1249481},
timestamp = {Mon, 15 Nov 2021 17:53:34 +0100},
biburl = {https://dblp.org/rec/conf/cicc/VenkataWTCHLTSL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HuttonCKMNPPPSS02,
author = {Michael D. Hutton and
Vinson Chan and
Peter Kazarian and
Victor Maruri and
Tony Ngai and
Jim Park and
Rakesh H. Patel and
Bruce Pedersen and
Jay Schleicher and
Sergey Y. Shumarayev},
editor = {Martine D. F. Schlag and
Steve Trimberger},
title = {Interconnect enhancements for a high-speed {PLD} architecture},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2002, Monterey, CA, USA, February 24-26, 2002},
pages = {3--10},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/503048.503050},
doi = {10.1145/503048.503050},
timestamp = {Sat, 28 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HuttonCKMNPPPSS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}

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